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doc. no. 101306c april 18, 2002 cx82100 cx82100 cx82100 cx82100 home network processor (hnp) home network processor (hnp) home network processor (hnp) home network processor (hnp) data sheet (preliminary) data sheet (preliminary) data sheet (preliminary) data sheet (preliminary) conexant proprietary information conexant confidential information dissemination, disclosure, or use of this information is not permitted without the written permission of conexant systems, inc.
cx82100 home network processor data sheet ii conexant proprietary and confidential information 101306c revision record revision date comments c 4/18/2002 revision c release. b 3/14/2002 revision b release. a 8/31/2001 initial release. ? 2001, 2002 conexant systems, inc. all rights reserved. information in this document is provided in connection with conexant systems, inc. (?conexant?) products. these materials are provided by conexant as a service to its customers and may be used for informational purposes only. conexant assumes no responsibility for errors or omissions in these materials. conexant may make changes to specifications and product descriptions at any time, without notice. conexant makes no commitment to update the information and shall have no responsibility whatsoever fo r conflicts or incompatibilities arising from future changes to its specifications and product descriptions. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. exce pt as provided in conexant?s terms and conditions of sale for such products, conexant assumes no liability whatsoever. these materials are provided ?as is? without warranty of any kind, either express or implied, relating to sale and/or use of conexant products including liability or warranties relating to fitness for a particular purpose, consequential or incidental damages, merchantability, or infringement of any patent, copyright or other intellectual property right. conexant further does not warrant the accuracy or completeness of the information, text, graphics or other items contained within these materials. conexant shall not be liable for any special, indirect, incidental, or consequential damages, including without limitation, lost revenues or lost profits, which may result from the use of these materials. conexant products are not intended for use in medical, lifesaving or life sustaining applications. conexant customers using or selling conexant products for use in such applications do so at their own risk and agree to fully indemnify conexant for any damages resulting from such improper use or sale. the following are trademarks of conexant systems, inc.: conexant?, the conexant c symbol, and ?what?s next in communications technologies??. product names or services listed in this publication are for identification purposes only, and m ay be trademarks of third parties. third-party brands and names are the property of their respective owners. arm, arm9tdmi, and thumb are registered trademarks, and arm940t and arm9 are trademarks, of arm limited. for additional disclaimer information, please consult conexant?s legal information posted at www.conexant.com, which is incorporated by reference. reader response: conexant strives to produce quality documentation and welcomes your feedback. please send comments and suggestions to tech.pubs@conexant.com. for technical questions, contact your local conexant sales office or field applications engineer.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information iii contents revision history ............................................................................................................... ........................... xiv 1 introduction .................................................................................................................. ....................... 1-1 1.1 scope....................................................................................................................... ...................................................1-2 1.2 features .................................................................................................................... ..................................................1-2 1.3 general hardware overview................................................................................................... ......................................1-3 1.3.1 advanced microcontroller bus architecture ................................................................................. ................1-6 1.3.2 arm940t processor ......................................................................................................... ..........................1-6 1.3.3 asb decoder ............................................................................................................... ................................1-6 1.3.4 asb arbiter............................................................................................................... ...................................1-7 1.3.5 asb masters............................................................................................................... .................................1-7 arm940t master................................................................................................................. ................1-7 dmac master .................................................................................................................... ..................1-7 host interface master .......................................................................................................... ................1-7 1.3.6 asb slaves ................................................................................................................ ..................................1-8 arm940t slave .................................................................................................................. .................1-8 external memory controller slave............................................................................................... .........1-8 asb-to-apb bridge/dmac ......................................................................................................... ..........1-8 internal rom ................................................................................................................... ....................1-8 internal ram ................................................................................................................... ....................1-8 1.3.7 apb functions ............................................................................................................. ................................1-9 emac interface ................................................................................................................. ...................1-9 usb interface.................................................................................................................. .....................1-9 general purpose input/output interface......................................................................................... ......1-9 clock generation............................................................................................................... ...................1-9 interrupt controller ........................................................................................................... ...................1-9 1.4 development kits ............................................................................................................ ............................................1-9 1.5 typical applications........................................................................................................ ...........................................1-10 1.5.1 typical home networking architecture ...................................................................................... ................1-10 1.6 references .................................................................................................................. ..............................................1-13 1.7 key words................................................................................................................... ..............................................1-14 1.8 conventions ................................................................................................................. .............................................1-15 1.8.1 data lengths .............................................................................................................. ...............................1-15 1.8.2 register descriptions ..................................................................................................... ...........................1-15
cx82100 home network processor data sheet iv conexant proprietary and confidential information 101306c 2 cx82100 hnp hardware interface ................................................................................................ ....... 2-1 2.1 cx82100 hnp hardware interface signals ...................................................................................... ............................2-1 2.1.1 cx82100-11/-12/-51/-52 signal interface and pin assignments ............................................................... ...2-1 2.1.2 cx82100-41/-42 signal interface and pin assignments....................................................................... ........2-1 2.1.3 cx82100 hnp signal definitions ............................................................................................ .....................2-1 2.2 cx82100 hnp electrical and environmental specifications..................................................................... ...................2-17 2.2.1 dc electrical characteristics ............................................................................................. .........................2-17 2.2.2 operating conditions, absolute maximum ratings, and power consumption............................................2-18 2.3 optional gpio and host signal usage ......................................................................................... ..............................2-19 2.4 interface timing and waveforms.............................................................................................. .................................2-21 2.4.1 external memory interface (sdram)......................................................................................... ................2-21 2.4.2 host interface timing ..................................................................................................... ...........................2-21 2.4.3 emac interface timing ..................................................................................................... .........................2-21 2.4.4 usb interface timing...................................................................................................... ...........................2-21 2.4.5 gpio interface timing ..................................................................................................... ..........................2-21 2.4.6 interrupt timing .......................................................................................................... ..............................2-22 2.4.7 clock reset timing........................................................................................................ ............................2-22 2.4.8 reset timing .............................................................................................................. ...............................2-22 2.5 package dimensions .......................................................................................................... .......................................2-23 3 hnp memory architecture ....................................................................................................... ............ 3-1 3.1 hnp memory map.............................................................................................................. .........................................3-1 3.2 starting addresses .......................................................................................................... ............................................3-3 3.2.1 arm vector table.......................................................................................................... ..............................3-3 3.3 endianness.................................................................................................................. ................................................3-4 3.4 boot procedure .............................................................................................................. .............................................3-4 4 dmac interface description.................................................................................................... ............. 4-1 4.1 dma channel definition ...................................................................................................... ........................................4-1 4.2 dma requests and data transfer.............................................................................................. ..................................4-1 4.3 control registers ........................................................................................................... .............................................4-2 4.4 dmac register memory map .................................................................................................... ..................................4-3 4.5 control register formats.................................................................................................... .........................................4-4 4.5.1 dmac x current pointer 1 (dmac_{x}_ptr1) .................................................................................. .............4-4 4.5.2 dmac x indirect/return pointer 1 (dmac_{x}_ptr2).......................................................................... ..........4-4 4.5.3 dmac x buffer size counter 1 (dmac_{x}_cnt1).............................................................................. ...........4-4 4.5.4 dmac x buffer size counter 2 (dmac_{x}_cnt2).............................................................................. ...........4-4 4.5.5 dmac x buffer size counter 3 (dmac_{x}_cnt3).............................................................................. ...........4-5 4.6 three basic modes of address generation ..................................................................................... .............................4-6 4.6.1 source or destination mode ................................................................................................ ........................4-6 4.6.2 circular buffer modes..................................................................................................... .............................4-6 direct circular buffer ......................................................................................................... ..................4-6 indirect circular pointer table................................................................................................ ..............4-7 4.6.3 linked list mode .......................................................................................................... ...............................4-9 embedded tail linked list descriptor mode ...................................................................................... ..4-9 indirect/table linked list descriptor mode..................................................................................... ...4-12
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information v 5 host interface description .................................................................................................... ............... 5-1 5.1 master mode ................................................................................................................. ..............................................5-1 5.1.1 host master mode interface signals ........................................................................................ ....................5-1 5.1.2 flash memory interface .................................................................................................... ...........................5-3 5.1.3 interfacing to other slave devices ........................................................................................ .......................5-3 5.1.4 host master mode dma engine............................................................................................... ....................5-3 asynchronous dma transfer mode ................................................................................................. ....5-3 isochronous dma transfer mode .................................................................................................. ......5-3 general dma information ........................................................................................................ ............5-4 5.1.5 host master mode timing (cx82100-11/-12/-51/-52) .......................................................................... .......5-5 host master mode read operation (accessing an external device) .....................................................5-5 host master mode write operation (accessing an external device) .....................................................5-5 5.1.6 host master mode timing (cx82100-41/-42).................................................................................. ............5-8 host master mode read operation (accessing an external device) .....................................................5-8 host master mode write operation (accessing an external device) .....................................................5-8 hrdy# description (cx82100-41/-42) ............................................................................................. ...5-9 5.2 host master mode register memory map ........................................................................................ .........................5-12 5.3 host master mode registers .................................................................................................. ...................................5-13 5.3.1 host control register (hst_ctrl: 0x002d0000).............................................................................. ........5-13 5.3.2 host master mode read-wait-state control register (hst_rwst: 0x002d0004) ....................................5-14 5.3.3 host master mode write-wait-state control register) (hst_wwst: 0x002d0008)..................................5-14 5.3.4 host master mode transfer control register (hst_xfer_cntl: 0x002d000c)........................................5-14 5.3.5 host master mode read control register 1 (hst_read_cntl1: 0x002d0010) .......................................5-14 5.3.6 host master mode read control register 2 (hst_read_cntl2: 0x002d0014) .......................................5-15 5.3.7 host master mode write control register 1 (hst_write_cntl1: 0x002d0018) .....................................5-15 5.3.8 host master mode write control register 2 (hst_write_cntl2: 0x002d001c).....................................5-15 5.3.9 host master mode peripheral size (mstr_intf_width: 0x002d0020) ...................................................5-15 5.3.10 host master mode peripheral handshake (mstr_handshake: 0x002d0024) (cx82100-41/-42) ...........5-16 5.3.11 host master mode dma source address (hdma_src_addr: 0x002d0028)...........................................5-16 5.3.12 host master mode dma destination address (hdma_dst_addr: 0x002d002c) ....................................5-16 5.3.13 host master mode dma byte count (hdma_bcnt: 0x002d0030) ............................................................5-16 5.3.14 host master mode dma timers (hdma_timers: 0x002d0034) ..............................................................5-16 6 external memory controller interface description .............................................................................. .6-1 6.1 pc100 compliant sdram interface............................................................................................. ................................6-1 6.2 available vendor sdram ics and features ..................................................................................... ............................6-3 6.3 supported configurations.................................................................................................... ........................................6-4 6.4 access cycles ............................................................................................................... ..............................................6-4 6.5 initialization.............................................................................................................. ...................................................6-4 6.6 refresh ..................................................................................................................... ..................................................6-4 6.7 read........................................................................................................................ ....................................................6-5 6.8 write ....................................................................................................................... ....................................................6-5 6.9 throughput .................................................................................................................. ...............................................6-5 6.10 emc i/o clock interface and timing ......................................................................................... ...................................6-6 6.11 sram interface ............................................................................................................. ..............................................6-7 6.12 emc register ............................................................................................................... ...............................................6-8 6.12.1 external memory control register (emcr: 0x00350010) ...................................................................... ......6-8
cx82100 home network processor data sheet vi conexant proprietary and confidential information 101306c 7 ethernet media access control interface description .......................................................................... 7 -1 7.1 mac frame format ............................................................................................................ .........................................7-2 7.2 parameterized values used in implementation ................................................................................. ...........................7-3 7.3 emac functional features.................................................................................................... .......................................7-4 7.4 emac architecture ........................................................................................................... ...........................................7-6 7.5 media independent interface (mii) ........................................................................................... ...................................7-7 7.6 emac interrupts............................................................................................................. .............................................7-8 7.7 tmac architecture ........................................................................................................... ...........................................7-9 7.7.1 transmit frame structure.................................................................................................. ..........................7-9 7.7.2 transmit descriptor....................................................................................................... ............................7-11 7.7.3 transmit status (tstat) ................................................................................................... ........................7-12 7.7.4 sequence of transmitter dma operation..................................................................................... ..............7-14 7.8 rmac architecture........................................................................................................... .........................................7-15 7.8.1 support for the detection of invalid mac frames ........................................................................... ...........7-15 condition 1 .................................................................................................................... ....................7-15 condition 2 .................................................................................................................... ....................7-15 condition 3 .................................................................................................................... ....................7-15 7.8.2 support for the reception without contention .............................................................................. ............7-15 7.8.3 support for the reception with contention ................................................................................. ..............7-16 7.8.4 address filtering......................................................................................................... ...............................7-16 setup frame .................................................................................................................... ..................7-16 perfect address filtering...................................................................................................... ..............7-16 example of a perfect address filtering setup frame ..........................................................................7-1 7 imperfect address filtering.................................................................................................... ............7-18 example of an imperfect address filtering setup frame ....................................................................7-20 address filtering modes ........................................................................................................ ............7-22 7.8.5 receive status handling ................................................................................................... .........................7-23 7.8.6 sequence of receiver dma operation ........................................................................................ ...............7-26 7.9 7-wire serial interface (7-ws) .............................................................................................. ....................................7-27 7.10 emac register memory map ................................................................................................... .................................7-28 7.11 emac registers ............................................................................................................. ...........................................7-29 7.11.1 emac x source/destination dma data register (e_dma_1: 0x00310000 and e_dma_2: 0x00320000).................................................................................................................... .........................7-29 7.11.2 emac x destination dma data register (et_dma_1: 0x00310020 and et_dma_2: 0x00320020) ...........7-29 7.11.3 emac x network access register (e_na_1: 0x00310004 and e_na_2: 0x00320004) ..............................7-30 7.11.4 emac x status register (e_stat_1: 0x00310008 and e_stat_2: 0x00320008) ..........................................7-33 7.11.5 emac x receiver last packet register (e_lp_1: 0x00310010 and e_lp_2: 0x00320010) ........................7-34 7.11.6 emac x interrupt enable register (e_ie_1: 0x0031000c and e_ie_2: 0x0032000c) .................................7-35 7.11.7 emac x mii management interface register (e_mii_1: 0x00310018 and e_mii_2: 0x00320018) .............7-36 8 usb interface description..................................................................................................... ............... 8-1 8.1 udc data path ............................................................................................................... .............................................8-3 8.1.1 usb transmit data path (endpoint in channel).............................................................................. .............8-3 8.1.2 usb receive data path (endpoint out channel) .............................................................................. ...........8-4 8.2 usb data flow ............................................................................................................... .............................................8-5
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information vii 8.3 udc core .................................................................................................................... ................................................8-6 8.3.1 endpoint buffer format.................................................................................................... ............................8-6 8.3.2 example of endpoint buffer encoding....................................................................................... ...................8-7 8.3.3 loading of the endptbuf configurations .................................................................................... ..................8-8 8.3.4 usb command handling ...................................................................................................... .......................8-9 8.4 usb dma interface ........................................................................................................... ........................................8-10 8.4.1 dma receive channel....................................................................................................... .........................8-10 8.4.2 dma transmit channel...................................................................................................... ........................8-12 8.5 interrupt endpoint .......................................................................................................... ...........................................8-14 8.6 summary of the endpoints.................................................................................................... ....................................8-14 8.7 usb register memory map ..................................................................................................... ..................................8-15 8.8 usb registers ............................................................................................................... ............................................8-16 8.8.1 usb source/destination dma data register 0 (u0_dma: 0x00330000)....................................................8-16 8.8.2 usb source/destination dma data register 1 (u1_dma: 0x00330008)....................................................8-16 8.8.3 usb source/destination dma data register 2 (u2_dma: 0x00330010)....................................................8-16 8.8.4 usb source/destination dma data register 3 (u3_dma: 0x00330018)....................................................8-16 8.8.5 usb destination dma data register (ut_dma: 0x00330020)...................................................................8 -17 8.8.6 usb configuration data register (u_cfg: 0x00330024) ....................................................................... ....8-17 8.8.7 usb interrupt data register (u_idat: 0x00330028) .......................................................................... .......8-17 8.8.8 usb control register 1 (u_ctr1: 0x0033002c) ............................................................................... ........8-18 8.8.9 usb control register 2 (u_ctr2: 0x00330030)............................................................................... .........8-20 8.8.10 usb control register 3 (u_ctr3: 0x00330034).............................................................................. ..........8-21 8.8.11 usb status (u_stat: 0x00330038) .......................................................................................... ................8-22 8.8.12 usb interrupt enable register (u_ier: 0x0033003c) ........................................................................ ........8-25 8.8.13 usb status register 2 (u_stat2: 0x00330040) .............................................................................. .........8-26 8.8.14 usb interrupt enable register 2 (u_ier2: 0x00330044) ..................................................................... ......8-28 8.8.15 udc time stamp register (udc_tsr: 0x0033008c) ............................................................................ ....8-29 8.8.16 udc status register (udc_stat: 0x00330090)............................................................................... .........8-29 8.9 usb dma control registers ................................................................................................... ...................................8-30 8.9.1 ep0_in transmit increment register (ep0_in_tx_inc: 0x00330048) ......................................................8-30 8.9.2 ep0_in transmit pending register (ep0_in_tx_pend: 0x0033004c)......................................................8-30 8.9.3 ep0_in transmit qword count register (ep0_in_tx_qwcnt: 0x00330050) ...........................................8-30 8.9.4 ep1_in transmit increment register (ep1_in_tx_inc: 0x00330054) ......................................................8-30 8.9.5 ep1_in transmit pending register (ep1_in_tx_pend: 0x00330058)......................................................8-31 8.9.6 ep1_in transmit qword count register (ep1_in_tx_qwcnt).................................................................8-3 1 8.9.7 ep2_in transmit increment register (ep2_in_tx_inc: 0x00330060) ......................................................8-31 8.9.8 ep2_in transmit pending register (ep2_in_tx_pend: 0x00330064)......................................................8-31 8.9.9 ep2_in transmit qword count register (ep2_in_tx_qwcnt).................................................................8-3 2 8.9.10 ep3_in transmit increment register (ep1_in_tx_inc: 0x0033006c)......................................................8-32 8.9.11 ep3_in transmit pending register (ep3_in_tx_pend: 0x00330070)......................................................8-32 8.9.12 ep3_in transmit qword count register (ep3_in_tx_qwcnt: 0x00330074) ...........................................8-32 8.9.13 ep_out receive decrement register (ep_out_rx_dec: 0x00330078)...................................................8-33 8.9.14 ep_out receive pending register (ep_out_rx_pend: 0x0033007c) ....................................................8-33 8.9.15 ep_out receive buffer size register (ep_out_rx_bufsize: 0x00330084)............................................8-33 8.9.16 ep_out receive qword count register (ep_out_rx_qwcnt: 0x00330080)..........................................8-33 8.9.17 usb receive dma watchdog timer register (usb_rxtimer: 0x00330094)............................................8-34 8.9.18 usb receive dma watchdog timer counter register (usb_rxtimercnt: 0x00330098)........................8-34 8.9.19 ep_out receive pending interrupt level register (ep_out_rx_pendlevel: 0x0033009c)...................8-34 8.9.20 usb control-status register (u_csr: 0x00330088) .......................................................................... .......8-35
cx82100 home network processor data sheet viii conexant proprietary and confidential information 101306c 9 general purpose input/output interface description............................................................................ 9-1 9.1 gpio pin description........................................................................................................ ...........................................9-1 9.2 gpio register memory map.................................................................................................... ....................................9-2 9.3 gpio registers.............................................................................................................. ..............................................9-3 9.3.1 gpio option register for gpio[39:37; 32] (gpio_opt: 0x003500b0) ........................................................9-3 9.3.2 gpio output enable register 1 for gpio[15:14; 8:5] (gpio_oe1: 0x003500b4) .........................................9-4 9.3.3 gpio output enable register 2 for gpio[31; 27:16] (gpio_oe2: 0x003500b8) ..........................................9-4 9.3.4 gpio output enable register 3 for gpio[39:37; 32] (gpio_oe3: 0x003500bc) ..........................................9-5 9.3.5 gpio data input register 1 for gpio[15:14; 8:5] (gpio_data_in1: 0x003500c0) .....................................9-5 9.3.6 gpio data input register 2 for gpio[31; 27:24; 22:16] (gpio_data_in2: 0x003500c4) ...........................9-6 9.3.7 gpio data input register 3 for gpio[39:37; 32] (gpio_data_in3: 0x003500c8) ......................................9-6 9.3.8 gpio data output register 1 for gpio[15:14; 8:5] (gpio_data_out1: 0x003500cc) ...............................9-7 9.3.9 gpio data output register 2 for gpio[31; 27:24; 22:16] (gpio_data_out2: 0x003500d0) .....................9-8 9.3.10 gpio data output register 3 for gpio[39:37; 32] (gpio_data_out3: 0x003500d4) ................................9-9 9.3.11 gpio interrupt status register 1 for gpio[15:14; 8:5] (gpio_isr1: 0x003500d8) ...................................9-10 9.3.12 gpio interrupt status register 2 for gpio[31; 27:24; 22:16] (gpio_isr2: 0x003500dc) .........................9-10 9.3.13 gpio interrupt status register 3 for gpio[39:37; 32] (gpio_isr3: 0x003500e0).....................................9-12 9.3.14 gpio interrupt enable register 1 for gpio[15:14; 8:5] (gpio_ier1: 0x003500e4) ...................................9-13 9.3.15 gpio interrupt enable register 2 for gpio[31; 27:24; 22:16] (gpio_ier2: 0x003500e8) .........................9-14 9.3.16 gpio interrupt enable register 3 for gpio[39:37; 32] (gpio_ier3: 0x003500ec) ....................................9-15 9.3.17 gpio interrupt polarity control register 1 for gpio[15:14; 8:5] (gpio_ipc1: 0x003500f0)......................9-16 9.3.18 gpio interrupt polarity control register 2 for gpio[31; 27:24; 22:16] (gpio_ipc2: 0x003500f4)............9-17 9.3.19 gpio interrupt polarity control register 3 for gpio[39:37; 32] (gpio_ipc3: 0x003500f8).......................9-18 9.3.20 gpio interrupt sensitivity mode register 1 for gpio[15:14; 8:5] (gpio_ism1: 0x003500a0)...................9-19 9.3.21 gpio interrupt sensitivity mode register 2 for gpio[31; 27:24; 22:16] (gpio_ism2: 0x003500a4).........9-20 9.3.22 gpio interrupt sensitivity mode register 3 for gpio[39:37; 32] (gpio_ism3: 0x003500a8)....................9-21 10 memory to memory transfer input/output ....................................................................................... . 10-1 10.1 operation .................................................................................................................. ................................................10-1 10.2 m2m register memory map.................................................................................................... ..................................10-3 10.3 m2m registers.............................................................................................................. ............................................10-3 10.3.1 memory to memory dma data register (m2m_dma: 0x00350000) .........................................................10-3 10.3.2 memory to memory dma transfer control/counter (m2m_cntl: 0x00350004) .........................................10-3 11 interrupt controller interface description ................................................................................... ....... 11-1 11.1 intc register memory map ................................................................................................... ...................................11-1 11.2 intc registers ............................................................................................................. .............................................11-1 11.2.1 interrupt level assignment register (int_la: 0x00350040) ................................................................. ....11-1 11.2.2 interrupt status register (int_stat: 0x00350044)......................................................................... ............11-2 11.2.3 interrupt set status register (int_setstat: 0x00350048).................................................................. ........11-4 11.2.4 interrupt mask register (int_msk: 0x0035004c)............................................................................ ..........11-4 11.2.5 interrupt mask status register (int_mstat: 0x00350090)................................................................... ......11-4 12 timers interface description................................................................................................. ............. 12-1 12.1 programmable periodic timers ............................................................................................... ..................................12-1 12.2 watchdog timer............................................................................................................. ...........................................12-1 12.3 timer usage/sdram refresh with other frequencies........................................................................... ....................12-2 12.4 timer registers memory map ................................................................................................. ..................................12-3
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information ix 12.5 timer registers............................................................................................................ .............................................12-3 12.5.1 timer 1 counter register (tm_cnt1: 0x00350020) ........................................................................... ........12-3 12.5.2 timer 2 counter register (tm_cnt2: 0x00350024) ........................................................................... ........12-3 12.5.3 timer 3 counter register (tm_cnt3: 0x00350028) ........................................................................... ........12-4 12.5.4 timer 4 counter register (tm_cnt4: 0x0035002c) ........................................................................... ........12-4 12.5.5 timer 1 limit register (tm_lmt1: 0x00350030)............................................................................. ..........12-4 12.5.6 timer 2 limit register (tm_lmt2: 0x00350034)............................................................................. ..........12-4 12.5.7 timer 3 limit register (tm_lmt3: 0x00350038)............................................................................. ..........12-5 12.5.8 timer 4 limit register (tm_lmt4: 0x0035003c)............................................................................. ..........12-5 13 clock generation interface description....................................................................................... ....... 13-1 13.1 pll normal mode ............................................................................................................ .........................................13-3 13.2 generated clocks ........................................................................................................... ...........................................13-3 13.3 pll register memory map.................................................................................................... ....................................13-5 13.4 pll registers.............................................................................................................. ..............................................13-5 13.4.1 fclk pll register (pll_f: 0x00350068).................................................................................... ..............13-5 13.4.2 bclk pll register (pll_b: 0x0035006c) .................................................................................... ............13-6 13.4.3 low power mode register (lpmr: 0x00350014)............................................................................... .......13-7 13.5 pll programming............................................................................................................ .........................................13-8 13.6 watchdog timer mode ........................................................................................................ ......................................13-9 13.7 pll bypass mode ............................................................................................................ .........................................13-9 14 register map summary ......................................................................................................... ............ 14-1 14.1 register type definition ................................................................................................... .........................................14-1 14.2 interface registers sorted by supported function........................................................................... ..........................14-2 14.3 interface registers sorted by address...................................................................................... .................................14-6
cx82100 home network processor data sheet x conexant proprietary and confidential information 101306c figures figure 1-1. cx82100 hnp major system interface ................................................................................. .........................1-3 figure 1-2. cx82100 hnp typical system interface ? residential gateway firewall plus router application ...................1-4 figure 1-3. cx82100 hnp typical system interface ? ethernet/homepna 2.0 bridge application ...................................1- 4 figure 1-4. cx82100 hnp block diagram.......................................................................................... ..............................1-5 figure 1-5. example of a residential gateway firewall plus router application .................................................. ...........1-11 figure 1-6. example of a homepna 2.0 bridge application........................................................................ ....................1-12 figure 2-1. cx82100-11/-12/-51/-52 hnp hardware interface signals .............................................................. ..............2-2 figure 2-2. cx82100-11/-12/-51/-52 hnp pin signals-196-pin fpbga ............................................................... ............2-3 figure 2-3. cx82100-41/-42 hnp hardware interface signals ...................................................................... ...................2-5 figure 2-4. cx82100-41/-42 hnp pin signals-196-pin fpbga ....................................................................... .................2-6 figure 2-5. external memory interface timing ................................................................................... ............................2-21 figure 2-6. package dimensions ? 196-pin 15 mm x 15 mm fpbga................................................................... ..........2-23 figure 3-1. hnp memory map ..................................................................................................... ....................................3-2 figure 3-2. little-endian mode addressing...................................................................................... ................................3-4 figure 3-3. boot procedure..................................................................................................... .........................................3-5 figure 4-1. address generation in direct circular buffer mode.................................................................. ......................4-6 figure 4-2. embedded tail linked list descriptor example....................................................................... .....................4-10 figure 4-3. indirect/table linked list descriptor example 1 .................................................................... ......................4-12 figure 4-4. indirect/table linked list descriptor example 2 .................................................................... ......................4-13 figure 5-1. host master mode signals........................................................................................... ..................................5-1 figure 5-2. little-endian mode data bus mapping ................................................................................ ...........................5-2 figure 5-3. waveforms for host master mode read operation (cx82100-11/-12/-51/-52)............................................. .5-6 figure 5-4. waveforms for host master mode write operation (cx82100-11/-12/-51/-52) ............................................ .5-7 figure 5-5. waveforms for host master mode read operation (cx82100-41/-42) ..................................................... ...5-10 figure 5-6. waveforms for host master mode write operation (cx82100-41/-42) .................................................... ....5-11 figure 6-1. sdram interface.................................................................................................... .......................................6-1 figure 6-2. emc clocking interface............................................................................................. .....................................6-6 figure 6-3. emc i/o timing ..................................................................................................... ........................................6-6 figure 7-1. mac sublayer partition, relationship to osi reference model ........................................................ ..............7-1 figure 7-2. ethernet mac frame format.......................................................................................... ................................7-2 figure 7-3. emac functional block diagram...................................................................................... ..............................7-6 figure 7-4. mii connector...................................................................................................... ..........................................7-7 figure 7-5. emac transmit frame structure ...................................................................................... ...........................7-10 figure 7-6. tmac dma operation for channel {x} = 1 or 3........................................................................ .....................7-14 figure 7-7. a perfect address filtering setup frame buffer ..................................................................... ......................7-17 figure 7-8. a circuit for dividing by g(x)..................................................................................... ..................................7-18 figure 7-9. imperfect address filtering........................................................................................ ..................................7-20 figure 7-10. example of imperfect filtering setup frame........................................................................ .......................7-21 figure 7-11. sequence of receiver dma operation ................................................................................ .......................7-26 figure 8-1. block diagram of the usb interface................................................................................. ..............................8-2 figure 8-2. usb transmit data flow ............................................................................................. ...................................8-3
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information xi figure 8-3. usb receive data flow.............................................................................................. ....................................8-4 figure 8-4. example of an usb device for hnp ................................................................................... ............................8-7 figure 8-5. loading of the endptbuf configurations ............................................................................. ...........................8-9 figure 8-6. dma channel supporting usb receive out endpoints ................................................................... ............8-10 figure 8-7. dma channels for usb transmit in endpoints......................................................................... ...................8-12 figure 9-1. gpio[x] interface.................................................................................................. .........................................9-1 figure 13-1. clock generation block diagram.................................................................................... ............................13-2 figure 13-2. clocks generated in the pll bypass mode ........................................................................... ...................13-10
cx82100 home network processor data sheet xii conexant proprietary and confidential information 101306c tables table 1-1. cx82100 order numbers, part numbers, and supported features ......................................................... ........1-1 table 2-1. cx82100-11/-12/-51/-52 hnp pin signals ? 196-pin fpbga ..........................................................................2-4 table 2-2. cx82100-41/-42 hnp pin signals ? 196-pin fpbga.......................................................................................2-7 table 2-3. cx82100 hnp pin signal definitions .................................................................................. ............................2-8 table 2-4. cx82100 hnp input/output type descriptions .......................................................................... ...................2-16 table 2-5. cx82100 hnp dc electrical characteristics ........................................................................... .......................2-17 table 2-6. cx82100 hnp operating conditions .................................................................................... .........................2-18 table 2-7. cx82100 hnp absolute maximum ratings................................................................................ ...................2-18 table 2-8. cx82100 hnp power consumption ....................................................................................... .......................2-18 table 2-9. cx82100 hnp recommended gpio and host signal use.................................................................... .........2-19 table 2-10. cx82100 hnp definitions of recommended gpio and host signals ....................................................... ...2-20 table 3-1. starting addresses for mapping asb slaves ........................................................................... ........................3-3 table 3-2. starting addresses for mapping apb slaves ........................................................................... ........................3-3 table 3-3. arm exception vector addresses ...................................................................................... .............................3-3 table 4-1. dma channel definition for dmac..................................................................................... .............................4-1 table 4-2. dma requests for apb peripherals .................................................................................... ............................4-2 table 4-3. dmac registers...................................................................................................... ........................................4-3 table 4-4. cluster descriptor table............................................................................................ ......................................4-7 table 4-5. received data packet................................................................................................ ......................................4-8 table 5-1. host master mode signals............................................................................................ ..................................5-2 table 5-2. chip select address ranges .......................................................................................... .................................5-3 table 5-3. timing for host master mode read operation based on a 100 mhz bclk (cx82100-11/-12/-51/-52)............5-6 table 5-4. timing for host master mode write operation based on a 100 mhz bclk (cx82100-11/-12/-51/-52) ...........5-7 table 5-5. timing for host master mode read operation based on a 100 mhz bclk (cx82100-41/-42) ......................5-10 table 5-6. timing for host master mode write operation based on a 100 mhz bclk (cx82100-41/-42)......................5-11 table 5-7. host master mode registers.......................................................................................... ...............................5-12 table 6-1. emc sdram interface signal descriptions............................................................................. ........................6-2 table 6-2. pc100 compliant mode register ....................................................................................... .............................6-2 table 6-3. available sdram vendors ............................................................................................. .................................6-3 table 6-4. allowed sdram configurations........................................................................................ ..............................6-4 table 6-5. sdram throughput.................................................................................................... ....................................6-5 table 6-6. hnp to sdram/sram interface signal mapping.......................................................................... ..................6-7 table 6-7. emc register........................................................................................................ ..........................................6-8 table 7-1. parameterized values implemented in emac ............................................................................ ......................7-3 table 7-2. transmit descriptor format .......................................................................................... ................................7-11 table 7-3. transmit status format .............................................................................................. ..................................7-12 table 7-4. setup frame buffer format ........................................................................................... ................................7-17 table 7-5. imperfect address filtering setup frame format ...................................................................... ....................7-19 table 7-6. hash index generated using ethernet crc algorithm................................................................... ................7-20 table 7-7. address filtering mode .............................................................................................. ...................................7-22 table 7-8. definition of rmac receive status ................................................................................... ............................7-24
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information xiii table 7-9. 7-ws interface signals .............................................................................................. ...................................7-27 table 7-10. emac registers ..................................................................................................... .....................................7-28 table 8-1. endpoint buffer format in udc core.................................................................................. .............................8-6 table 8-2. example of the endptbuf encoding .................................................................................... .............................8-7 table 8-3. dma channel supporting usb receive out endpoints .................................................................... ............8-10 table 8-4. status qword for receive (out) endpoint apb buffers................................................................. ................8-11 table 8-5. dma channels for usb transmit in endpoints .......................................................................... ...................8-12 table 8-6. descriptor qword for transmit (in) endpoint tx dma packet buffer .................................................... ........8-13 table 8-7. status qword for transmit (in) endpoint tx dma packet buffer........................................................ ...........8-13 table 8-8. udc endpoints....................................................................................................... .......................................8-14 table 8-9. usb registers....................................................................................................... ........................................8-15 table 8-10. ep_out receive pending level register .............................................................................. ......................8-34 table 9-1. gpio registers ...................................................................................................... .........................................9-2 table 10-1. m2m transfer example 1............................................................................................. ...............................10-1 table 10-2. m2m transfer example 2............................................................................................. ...............................10-2 table 10-3. m2m transfer example 3............................................................................................. ...............................10-2 table 10-4. m2m registers ...................................................................................................... .....................................10-3 table 11-1. intc registers..................................................................................................... .......................................11-1 table 12-1. timer resolution and sdram refresh rate ............................................................................ ...................12-2 table 12-2. timer registers .................................................................................................... ......................................12-3 table 13-1. fclkio/gpio39 pin usage control .................................................................................... .........................13-1 table 13-2. bclkio/gpio38 pin usage control.................................................................................... .........................13-1 table 13-3. fclk pll generated clocks.......................................................................................... ..............................13-4 table 13-4. bclk pll generated clocks .......................................................................................... .............................13-4 table 13-5. fclk pll generated clocks programming examples ..................................................................... ............13-4 table 13-6. bclk pll generated clocks programming examples ..................................................................... ............13-4 table 13-7. pll register memory map ............................................................................................ .............................13-5 table 13-8. desired frequencies and programming parameters..................................................................... ...............13-8 table 13-9. clocking requirements .............................................................................................. .................................13-9 table 14-1. register type definition........................................................................................... ...................................14-1 table 14-2. cx82100 interface registers sorted by supported function ........................................................... ............14-2 table 14-3. cx82100 interface registers sorted by address...................................................................... ...................14-6
cx82100 home network processor data sheet xiv conexant proprietary and confidential information 101306c revision history changes incorporated in doc. no. 101306c 1. table 1-1: revised order no. 2. figure 2-3: revised pin n13 to vsso rather than vddo for cx82100-41/-42. 3. figure 2-4: revised pin n13 to vsso rather than vddo for cx82100-41/-42. 4. table 2-2: revised pin n13 to vsso rather than vddo for cx82100-41/-42. 5. table 2-3: revised pin n13 to vsso rather than vddo for cx82100-41/-42. 6. table 2-9: revised gpio20 to lan 1 reset (lan1_rst#) rather than gpio5. 7. table 2-10: revised gpio20 to lan 1 reset (lan1_rst#) rather than gpio5. changes incorporated in doc. no. 101306b 1. chapter 1: revised maximum mips, added hrdy# paragraph, and added cx82100 hnp configuration differences to the introduction. 2. table 1-1: added models numbers and expanded table. 3. section 1.5: deleted. 4. section 2.1.1: revised section with applicability to cx82100-11/-12/-51/-52. 5. section 2.1.2: added section with applicability to cx82100-41/-42. 6. section 2.1.3: added heading. 7. figure 2-1: corrected pin number signals for m13 [hc08 (hrd#)], m12 [hc09 (hwr#)], and p14 [hc00 (hcs0#)/gpio32]. 8. figure 2-1, figure 2-2, and table 2-1: revised with applicability to cx82100-11/- 12/-51/-52. 9. figure 2-3, figure 2-4, and table 2-2: added with applicability to cx82100-41/-42. 10. table 2-3: revised vsso pins, revised usbp and usbn interface resistor value, hc00 pins, and hc10 pins, and gpio17 and gpio6 reset state. 11. section 2.3 (old): deleted. 12. figure 2-6: corrected signal labels. 13. table 5-1: rearranged. 14. section 5.1.5: added reference to cx82100-11/-12/-51/-52. 15. section 5.1.6: added new section applicable to cx82100-41/-42. 16. section 5.3.10: added register description. 17. section 13.1: added pll_f 168 mhz maximum operating frequency. 18. table 13-3: added pll_f 168 mhz maximum operating frequency. 19. table 13-5: added pll_f 168 mhz maximum operating frequency. 20. section 13.4.1: revised bits 25:24 (pll_f_cr) description to add 84 mhz. 21. table 13-8: added example 6 for 168 mhz desired frequency.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 1-1 1 introduction the conexant? cx82100 home network processor (hnp) is a single-chip, 185 mips high performance, arm940t-based processor integrated with multiple network interface hardware functions and packaged into a 196-pin fpbga. embedded firmware supports complete networking system solutions in a wide variety of commercial, industrial, business, soho, and home applications with appropriate host software. typical applications include a residential gateway (rg) with network address translation (nat)/firewall services, or a homepna 2.0 or homeplug 1.0 bridge when the cx82100 hnp is combined with a standard 10/100 ethernet phy or home networking phy such as conexant?s cx24611 homepna 2.0 phy/afe. the cx82100 hnp is available in different models to support basic functions, programmable hrdy# polarity for 802.11b applications, higher throughput (higher fclk frequency), and ability to run intoto firewall software (table 1-1). table 1-1. cx82100 order numbers, part numbers, and supported features supported functions home network processor (hnp) [196-pin fpbga] order no./part no. programmable hrdy# polarity for 802.11b wireless interface max clock speed (fclk) supports intoto firewall software cx82100-11 no 144 mhz no CX82100-12 no 144 mhz yes cx82100-51 no 168 mhz no cx82100-52 no 168 mhz yes cx82100-41* yes 168 mhz no cx82100-42* yes 168 mhz yes * recommended for new designs. cx82100 hnp configuration differences: 1. cx82100-11 supports basic functions. hrdy#, for wireless applications, is not supported. the cx82100-11 supports the following two signals on the indicated pins (different from the cx82100-41): p13 = vss0 and p14 = hc00 (hcs0#)/gpio32 (see section 2.1.1). 2. CX82100-12 supports basic functions and intoto firewall software. same pinout as the cx82100-11. 3. cx82100-51 supports basic functions and higher frequency operation (fclk to 168 mhz). same pinout as the cx82100-11. 4. cx82100-52 supports basic functions, higher frequency operation (fclk to 168 mhz), and intoto firewall software. same pinout as the cx82100-11 and cx82100- 12. 5. cx82100-41 supports basic functions and programmable hrdy# polarity for wireless applications (see section 5.1.6). the cx82100-41 supports the following two signals on the indicated pins (different from the cx82100-11): p13 = hc00 (hcs0#)/gpio32 and p14 = hc10 (hrdy#) (see section 2.1.2). recommended for new designs.
cx82100 home network processor data sheet 1-2 conexant proprietary and confidential information 101306c 6. cx82100-42 supports basic functions, programmable hrdy# polarity for wireless applications and intoto firewall software. same pinout as the cx82100-41. recommended for new designs. 1.1 scope this document describes the cx82100 hnp hardware architecture. 1.2 features ? single-chip, high-performance processor with integrated network interfaces ? arm940t processor ? advanced microcontroller bus architecture (amba) with two internal busses ? advanced system bus (asb) ? advanced peripheral bus (apb) ? 16k x 32 internal rom ? 8k x 32 internal ram ? external memory controller (emc) ? two identical 10/100 mbps ieee 802.3 ethernet media access controllers (emacs) with mii/7-ws interfaces ? usb 1.1 slave interface ? general purpose input/output (gpio) signals ? timers ? interrupt controller (intc) ? clock generators ? arm940t processor ? arm9tdmi core ? advanced system bus (asb) interface ? advanced peripheral bus (apb) interface ? separate 4 kb instruction and 4 kb data caches ? write-back cache scheme and write buffer optimize performance and minimize asb traffic ? five-stage pipeline with fetch, decode, execute, memory and write stages ? ?trackingice? mode allows a conventional ice (in-circuit emulator) mode of operation ? dual media independent interface (mii) interface to 10/100 ethernet phy ? host parallel expansion bus interface to flash rom and other devices ? parallel interface to sdram/sram ? jtag interface ? 22 general purpose i/o lines (13 available for application use, 6 available for application use if optional signals for eeprom, host parallel expansion bus, and clock are not used, and 3 dedicated to system signals) ? 196-pin fpbga
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 1-3 1.3 general hardware overview the major cx82100 hnp internal components (also referred to as blocks or functions) and external interfaces of the cx82100 hnp are illustrated in figure 1-1. a typical system interface for a residential gateway firewall plus router application using the cx82100 hnp is illustrated in figure 1-2. a typical system interface for an ethernet/homepna 2.0 bridge application using the cx82100 hnp is illustrated in figure 1-3. the major internal and external cx82100 interconnection signal paths are illustrated in figure 1-4. figure 1-1. cx82100 hnp major system interface 101306_065 control logic arm940t processor cx82100 home network processor (hnp) host interface random access memory (ram) read-only memory (rom) external memory controller (emc) universal serial bus (usb) interface general purpose input/output (gpio) interface sdram or sram host parallel expansion bus mii/7ws ethernet media access controller 1 (emac 1) usb ethernet media access controller 2 (emac 2) mii/7w s ethernet or cx24611 homepna 2.0 phy/afe (optional) ethernet or cx24611 homepna 2.0 phy/afe or 4-port switch (optional) flash rom pc or hub (optional) eeprom other peripherals
cx82100 home network processor data sheet 1-4 conexant proprietary and confidential information 101306c figure 1-2. cx82100 hnp typical system interface ? residential gateway firewall plus router application 101306-070 control logic arm940t processor cx82100 home network processor (hnp) host interface random access memory (ram) read-only memory (rom) external memory controller (emc) universal serial bus (usb) interface general purpose input/output (gpio) interface sdram or sram flash rom host parallel expansion bus mii lan rj-45 ethernet media access controller 1 (emac 1) usb ethernet media access controller 2 (emac 2) eeprom 10/100 ethernet interface devices 1 + 4-port switch lan rj-45 lan rj-45 lan rj-45 10/100 ethernet interface device mii wan rj-45 figure 1-3. cx82100 hnp typical system interface ? ethernet/homepna 2.0 bridge application 10/100 ethernet interface device 101306-002 control logic arm940t processor cx82100 home network processor (hnp) host interface random access memory (ram) read-only memory (rom) external memory controller (emc) universal serial bus (usb) interface general purpose input/output (gpio) interface sdram or sram mii lan rj-11 mii wan rj-45 ethernet media access controller 1 (emac 1) cx24611 homepna 2.0 phy/afe 100-pin tqfp usb ethernet media access controller 2 (emac 2) eeprom flash rom host parallel expansion bus
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 1-5 figure 1-4. cx82100 hnp block diagram 101306-003 asb arbiter asb-to-apb bridge/dmac rom (16k x 32) asb decoder host interface sm/s external sdram/ sram ram (8k x 32) s arm940t processor arm9tdmi core asb interface data cache write-back buffer instruction cache system control emc s m/s irq# fiq# emac 10/100baset mii/7w s to lan/wan phy interrupt controller (intc) timers usb interface usb to pc or usb hub gpio interface jtag clock generation (pll) fclk bclk pclk clki pllbp fclkio bclkio eeprom serial i/f emac 10/100baset i/o control/status host parallel expansion bus to flash rom and other mii/7w s to lan/wan phy cx82100 hnp advanced system bus (asb) master/slave (m/s) advanced peripheral bus (apb)
cx82100 home network processor data sheet 1-6 conexant proprietary and confidential information 101306c 1.3.1 advanced microcontroller bus architecture the hnp internal architecture is based on the advanced microcontroller bus architecture (amba) which defines two internal busses, the advanced system bus (asb) and the advanced peripheral bus (apb). ? the 32-bit asb is a high performance, burst-mode, pipelined bus, which connects multiple bus masters. the asb supports internal interfaces to functions (blocks) such as processor, on-chip memory, external memory controller, and dma controller. ? the 64-bit apb connects peripheral interface blocks to the asb through the asb- to-apb bridge/dmac and is designed for minimal power consumption and reduced complexity to support the system?s peripheral functions such as timers, emacs, and the usb interface. there are three other components of the amba system: the asb decoder, asb arbiter, and the asb-to-apb bridge. ? the asb decoder decodes the addresses for all the asb slave devices. ? the asb arbiter assigns the asb ownership to asb masters. ? all apb devices are accessible by asb masters through the asb-to-apb bridge. 1.3.2 arm940t processor the hnp uses an arm940t harvard load/store architecture cached processor macrocell with a high performance 32-bit risc-based arm9tdmi core. the "tdmi" stands for t humb 16-bit compressed instruction set, d ebug extensions, m ultiplier enhanced, and i ce extension. separate 4 kb instruction and 4 kb data caches and a memory protection unit allow the memory to be segmented and protected in a simple manner. a write-back cache scheme and write buffer are used to optimize performance and minimize asb traffic. the arm940t uses a 5-stage pipeline consisting of fetch, decode, execute, memory and write stages. the arm940t interfaces to the other internal hnp blocks using unified address and data busses compatible with the amba bus architecture. the arm940t also has a ?trackingice? mode that allows a conventional ice (in-circuit emulator) mode of operation. the arm9tdmi core has two active-low and level-sensitive interrupt inputs, fiq# and irq#, which can occur asynchronously. the fiq# is higher priority than irq# in that it is serviced first when both interrupts assert simultaneously. servicing an fiq# disables irq# until the fiq# handler exits or re-enables irq#. an interrupt handler must always clear the source of the interrupt. the vector addresses for irq# and fiq# are 0x00000018 and 0x0000001c, respectively. 1.3.3 asb decoder the asb decoder performs the address decoding and selects slaves appropriately.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 1-7 1.3.4 asb arbiter the asb arbiter performs arbitration on the asb to ensure that only one asb master at a time is allowed to initiate data transfers. no arbitration scheme is enforced, therefore, either 'highest priority' or 'fair' access algorithms may be implemented, depending on the application requirements. 1.3.5 asb masters an asb master can initiate read and write operations by providing address and control information. the hnp contains three bus masters: the arm940t, the host interface, and the dmac. only one bus master is allowed to actively use the asb at any one time. the dmac is both an asb master and an apb master. arm940t master the arm940t master transfers data to and from the internal rom, internal sram, the asb-to-apb bridge, and the external sdram/sram via the emc. the arm940t master also transfers configuration register information directly to and from the dmac. dmac master the dmac master transfers data to and from the external sdram/sram via the emc. the emc is the only asb slave accessed by the dmac master. the dmac is integrated with the asb-to-apb bridge because the dmac is both an asb master and an apb master. data transferred on the asb is always a dword (32 bits). however, data transferred on the apb is always a qword (64 bits) which requires valid data on the entire 64-bit apb data bus. host interface master the host interface master transfers data over the host parallel expansion bus to and from external flash rom and an optional peripheral (e.g., uart) via an internal memory-mapped register set using two chip select/gpio signals. the host interface master operates asynchronously. the host interface master can also be used as the test interface controller (tic) bus master. the tic is a low gate-count test interface module which allows externally applied test vectors to be converted into internal bus transfers. the tic can also be used to read and write registers within the hnp from the external host interface pins. the tic uses a minimal 3-wire handshake mechanism (treqa, treqb, and tack) to control the application of test vectors and the data path of the emc.
cx82100 home network processor data sheet 1-8 conexant proprietary and confidential information 101306c 1.3.6 asb slaves asb slaves respond to read or write operations within a given address-space range. a bus slave signals the success, failure, or waiting of the data transfer back to the active master. the asb slaves in the hnp asic are the arm940t (test mode only), emc, asb-to- apb bridge/dmac, internal rom, and internal sram. detailed discussion of the amba signals and protocols may be found in reference [3]. arm940t slave the arm940t slave has one 32-bit test-mode register that can be accessed by the tic during test mode. external memory controller slave the external memory controller (emc) controls all external sdram/sram accesses. the sdram/sram is programmed by the emc to transfer a burst of four data bytes. the configuration registers for the emc reside in the host control register (hst_ctrl) and the external memory control register (emcr). the sdram refresh controller is internal to the emc. the emc simply asserts the wait response to the asb if it is deselected (by the asb decoder) during the refresh. the master requesting the memory access is held off with wait states for the duration of the refresh operation. asb-to-apb bridge/dmac the asb-to-apb bridge converts asb transfers into a suitable format for the slave devices on the apb. the bridge provides latching of all address, data, and control signals, as well as provides a second level of decoding to generate slave select signals for the apb peripherals. the bridge is a slave on the asb and a master on the apb. all peripherals on the apb are slaves only. as an asb slave, the dmac is accessed by the arm940t and the host interface (including the tic asb master in test mode). obviously, the master portion of the dmac also has access, not via the asb but internal to the dmac module. note that the dmac is also a bus master on the apb. internal rom the internal 16k x 32 rom provides high-speed read-only program and data for the arm940t. the arm940t uses this internal rom or external flash rom to run the boot code upon the de-assertion of the reset signal. the internal rom code configures the udc with configuration data read from an optional i2c eeprom or internal rom. the internal rom code initiates udc setup by communicating to the i2c eeprom using the i2c_data (gpio15) and i2c_clock (gpio16) pins. based on the signature byte read from the i2c eeprom, the hnp uses either i2c eeprom data or internal rom data to set up the udc. see section for additional information. internal ram the internal 8k x 32 ram provides high-speed read-write program and data for the arm940t.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 1-9 1.3.7 apb functions the advanced peripheral bus (apb) provides signaling for i/o functions. emac interface dual media independent interface (mii) or 7-wire serial (7-ws) interfaces, controlled by two identical hnp 10/100baset ethernet mac (emac) blocks, optionally connect interchangeably to devices such as an ethernet transceiver phy, conexant cx24611 homepna 2.0 afe/phy, conexant cx11647 homeplug 1.0 device. usb interface the usb controlled by the hnp usb interface optionally connects to a pc or usb hub. this interface complies with the universal serial bus specification rev. 1.1 and operates at usb full speed (12 mbps). it acts as a usb slave device only, i.e., it cannot act as a root hub). general purpose input/output interface bidirectional general purpose input/output (gpio) lines are controlled by the hnp gpio interface. most of these gpio lines are used for the interfaces mentioned above in a fully configured system. clock generation the clock generation block generates internal and external clocks using two programmable, fractional multiply phase locked loop (pll) blocks, fclk_pll and bclk_pll. included in each block is the actual pll circuit including a voltage- controlled oscillator (vco), and post-pll generation logic which divides the output of each pll to create a series of sub-multiple clocks. interrupt controller all peripheral interrupt sources are routed through the interrupt controller (intc) and reduced to one of two active low inputs to the arm940t processor, fast interrupt (fiq#) or regular interrupt (irq#), as selected in the interrupt level assignment register (int_la). no hardware-assisted priority scheme is implemented in the hnp other than fiq# having a higher priority than irq#. the system software must implement the priority scheme for individual interrupts in the fiq# and irq# exception handlers. 1.4 development kits please contact a local conexant sales office for information about available development kits using the cx82100 hnp.
cx82100 home network processor data sheet 1-10 conexant proprietary and confidential information 101306c 1.5 typical applications typical applications include: ? firewall/router products ? homepna bridge products ? usb bridge products ? cable modem bridge products ? dsl modem bridge products ? residential gateway ? proxy servers 1.5.1 typical home networking architecture typical home networking architecture for a residential gateway firewall plus router box with an installed cx82100 hnp-based ethernet-to-ethernet interface is illustrated in figure 1-5. this box allows multiple home pcs to access the internet through a single point of connection. all the home pcs connect to the in-house rj-45 wiring using the cx82100 hnp-based ethernet interface. typical home networking architecture for a homepna 2.0 bridge box with an installed cx82100 hnp-based ethernet-to-homepna 2.0 interface is illustrated in figure 1-6. this box allows multiple home pcs and peripherals to access the internet through a single point of connection. all the home pcs and peripherals connect to the in-house rj- 11 wiring using the cx82100 hnp-based homepna 2.0 interface.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 1-11 figure 1-5. example of a residential gateway firewall plus router application broadband access device home pc 101306_069 residential gateway (rg) firewall plus router using the cx82100 hnp ethernet (rj45) ethernet network server network server public networks home pc home pc home pc rj45 rj45
cx82100 home network processor data sheet 1-12 conexant proprietary and confidential information 101306c figure 1-6. example of a homepna 2.0 bridge application rj-11 101306_001 ethernet homepna 2.0 home pna 2.0 bridge using the cx82100 hnp rj-45 phone fax homepna 2.0 phone line network printer scanner home pc home pc laptop computer network server network server public networks broadband access device
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 1-13 1.6 references [1] arm9tdmi data sheet, november, 1997, arm limited. [2] arm940t data sheet, november, 1997, arm limited. [3] amba?advanced microcontroller bus architecture specification, april, 1997, arm limited. [4] ansi/ieee 802.3, reference number iso/iec 8802-3, part 3: carrier sense multiple access with collision detection (csma/cd) access method and physical layer specifications, fifth edition, 1996-07-29. [5] ansi/ieee 802.3u, media access control (mac) parameters, physical layer, medium attachment units, and repeater for 100 mb/s operation, type 100base- t (clauses 21-30), 1995. [6] pc sdram specification, revision 1.63, october 1998, intel. [7] cx82110 xdsl ready home network processor (hnp) data sheet, doc. no. 101545, conexant. [8] cx24611 homepna 2.0 phy/afe data sheet, doc. no. 100633, conexant.
cx82100 home network processor data sheet 1-14 conexant proprietary and confidential information 101306c 1.7 key words 7-ws or 7ws 7-wire serial interface afe analog front end amba advanced microprocessor bus architecture apb advanced peripheral bus arm advanced risk microcontroller asb advanced system bus asic application specific integrated circuit crc cyclic redundancy check dmac direct memory access controller emac ethernet medium access control emc external memory controller fifo first-in-first-out gpio general purpose i/o gpsi general purpose serial interface homepna home phoneline networking alliance homeplug homeplug power line alliance ice in circuit emulator/emulation lsb least significant bit lsb least significant byte mac media access control mii media independent interface msb most significant bit msb most significant byte osi open systems interconnection phy physical layer soho small office home office sta station management entity tic test interface controller
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 1-15 1.8 conventions 1.8.1 data lengths qword 64-bits dword 32-bits word 16-bits byte 8 bits nibble 4 bits 1.8.2 register descriptions register type description ro read-only wo write-only rw read/write rw* read/write, but data may not be same as written at a later time rr same as rw, but writing a 1 resets corresponding bit location, writing 0 has no effect rwp read-only, write-only shared port, data written cannot be read. only accessible by dmac wd write-only, operates on other data entering register
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cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 2-1 2 cx82100 hnp hardware interface 2.1 cx82100 hnp hardware interface signals 2.1.1 cx82100-11/-12/-51/-52 signal interface and pin assignments cx82100-11/-12/-51/-52 hnp hardware interface signals are shown in figure 2-1. cx82100-11/-12/-51/-52 hnp pin signals are shown in figure 2-2 and are listed in table 2-1. note: the cx82100-11/-12/-51/-52 supports the following two signals on the indicated pins (different from the cx82100-41/-42): p13 = vss0 and p14 = hc00 (hcs0#)/gpio32 (see section 2.1.1). other pinouts are the same as the cx82100-41/-42. 2.1.2 cx82100-41/-42 signal interface and pin assignments cx82100-41/-42 hnp hardware interface signals are shown in figure 2-3. cx82100-41/-42 hnp pin signals are shown in figure 2-4 and are listed in table 2-2. note: the cx82100-41/-42 supports the following two signals on the indicated pins (different from the cx82100-11/-12/-51/-52): p13 = hc00 (hcs0#)/gpio32 and p14 = hc10 (hrdy#) (see section 2.1.2). other pinouts are the same as the cx82100-11/-12/-51/-52. 2.1.3 cx82100 hnp signal definitions cx82100 hnp hardware interface signals are defined in table 2-3. cx82100 hnp input/output types are described in table 2-4. cx82100 hnp dc electrical characteristics are listed in table 2-5.
cx82100 home network processor data sheet 2-2 conexant proprietary and confidential information 101306c figure 2-1. cx82100-11/-12/-51/-52 hnp hardware interface signals em1_col em1_crs em1_mdc em1_mdio em1_rx_clk em1_rxd0 em1_rxd1 em1_rxd2 em1_rxd3 em1_rxdv em1_rxer em1_tx_clk em1_tx_en em1_txd0 em1_txd1 em1_txd2 em1_txd3 em1_txer em2_col em2_crs em2_mdc em2_mdio em2_rx_clk em2_rxd0 em2_rxd1 em2_rxd2 em2_rxd3 em2_rxdv em2_rxer em2_tx_clk em2_tx_en em2_txd0 em2_txd1 em2_txd2 em2_txd3 em2_txer usbp usbn usb_pwr_det (gpio22)* clki hrst# vgg vdd vdda vddo vss vssa vsso tst0 tst1 tst2 tst3 pllbp bopt (gpio14)* treqa gpio5 gpio6 gpio7 gpio8 gpio17 gpio18 gpio19 gpio20 gpio21 gpio24 gpio25 gpio26 gpio27 gpio31 bclkio/gpio38 fclkio/gpio39 g1 g2 k8 m8 g5 h4 h3 h1 h2 l7 p8 e1 f1 f2 f5 f3 e4 g3 b8 j12 b6 a6 c8 a14 a7 b7 e7 c7 d7 l13 j13 m14 k12 l12 l14 k14 d9 e8 c9 j2 n14 h6 h7, h8 g6 a12, b3, b5, d1, d14, f6, f9, f12, h10, j7, k7, k11, n5, , n9, n11, n13, p1 g7, g8 h5 a5, b9, b11, d8 d12, f4, g9, h11 k13, l2, n8, p2 p5, p9, p11, p13, c4 c5 b4 a4 d4 j3 k4 k5 e6 d6 e5 d5 a3 a2 b2 b1 c3 a1 m7 a8 g4 c6 j5 j1 +3.3v had00 had01 had02 had03 had04 had05 had06 had07 had08 had09 had10 had11 had12 had13 had14 had15 hc01 hc02 hc03 hc04 hc05 hc06 hc07 had16 had17 had18 had19 had20 had21 had22 had23 had24 had25 had26 had27 had28 had29 hc08 (hrd#) hc09 (hwr#) hc00 (hcs0#)/gpio32 had31 (hcs4#)/gpio37 md00 md01 md02 md03 md04 md05 md06 md07 md08 md09 md10 md11 md12 md13 md14 md15 ma00 ma01 ma02 ma03 ma04 ma05 ma06 ma07 ma08 ma09 ma10 ma11 mm0 mm1 mb0 mb1 mras# mcas# mw e# mcs# mclk mcke i2c_data (gpio15)** i2c_clock (gpio16)** trst# tck tms tdi tdo nc nc nc nc nc p12 n12 l11 j10 m11 l10 k10 l9 m10 p10 n10 j9 k9 l8 m9 n7 p7 l6 p6 n6 k6 m6 l5 m5 l4 p4 n4 m4 p3 n3 m3 n1 n2 m1 m2 l1 l3 m13 m12 p14 j8 f11 e13 f10 f14 g11 f13 g10 g14 h9 g12 g13 h14 j11 h13 h12 j14 a10 b10 d10 c10 a11 f8 c11 d11 b12 a13 c12 b13 e11 e10 a9 e9 d13 c13 b14 c14 e14 e12 e2 e3 j4 k2 j6 k1 k3 c1 c2 d2 d3 f7 101306_066 cx82100 (-11/-12/-51/-52) home network processor (hnp) 196-pin fpbga sdram or sram media independent interface 1 (mii 1)/ 7-wire serial interface (7-ws1) clock reset circuit jtag +3.3v or +5v (clamp) +1.8v +1.8v (through filter) parallel expansion bus d00 d01 d02 d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 rd# we# cs0# (flash) d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 dqmh dqml ba0 ba1 ras# cas# we# cs# clke clk sda scl usb interface media independent interface 2 (mii 2)/ 7-wire serial interface (7-ws2) serial eeprom (optional) col crs mdc mdio rx_clk rxd0 rxd1 rxd2 rxd3 rxdv rxer tx_clk tx_en txd0 txd1 txd2 txd3 txer col crs mdc mdio rx_clk rxd0 rxd1 rxd2 rxd3 rxdv rxer tx_clk tx_en txd0 txd1 txd2 txd3 txer * dedicated gpio signal. ** may be assigned to different application use if not used for indicated function. nc 4.7k 4.7k application dependent nc
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 2-3 figure 2-2. cx82100-11/-12/-51/-52 hnp pin signals-196-pin fpbga a1 b1 c1 d1 e1 f1 g1 h1 j1 k1 l1 m1 n1 p1 12345678 91011121314 a2 b2 c2 d2 e2 f2 g2 h2 j2 k2 l2 m2 n2 p2 a3 b3 c3 d3 e3 f3 g3 h3 j3 k3 l3 m3 n3 p3 a4 b4 c4 d4 e4 f4 g4 h4 j4 k4 l4 m4 n4 p4 a5 b5 c5 d5 e5 f5 g5 h5 j5 k5 l5 m5 n5 p5 a6 b6 c6 d6 e6 f6 g6 h6 j6 k6 l6 m6 n6 p6 a7 b7 c7 d7 e7 f7 g7 h7 j7 k7 l7 m7 n7 p7 a10 b10 c10 d10 e10 f10 g10 h10 j10 k10 l10 m10 n10 p10 a8 b8 c8 d8 e8 f8 g8 h8 j8 k8 l8 m8 n8 p8 a9 b9 c9 d9 e9 f9 g9 h9 j9 k9 l9 m9 n9 p9 a11 b11 c11 d11 e11 f11 g11 h11 j11 k11 l11 m11 n11 p11 a12 b12 c12 d12 e12 f12 g12 h12 j12 k12 l12 m12 n12 p12 a13 b13 c13 d13 e13 f13 g13 h13 j13 k13 l13 m13 n13 p13 a14 b14 c14 d14 e14 f14 g14 h14 j14 k14 l14 m14 n14 p14 a b c d e f g h j k l m n p gpio24 gpio20 nc vddo em1_tx_clk em1_tx_en em1_col em1_rxd2 fclkio/gpio39 tdi had28 had26 had24 vddo gpio18 gpio19 nc nc i2c_data (gpio15) em1_txd0 em1_crs em1_rxd3 clki tck vsso had27 had25 vsso top view 101306_067 gpio17 vddo gpio21 nc gpio16 em1_txd2 em1_txer em1_rxd1 pllbp tdo had29 had23 had22 had21 tst2 tst1 vsso tst3 em1_txd3 vsso gpio27 em1_rxd0 trst# bopt (gpio14) had17 had20 had19 had18 vsso vddo tst0 gpio8 gpio7 em1_txd1 em1_rx_clk vssa bclkio/gpio38 treqa hc07 had16 vddo vsso em2_mdio em2_mdc gpio31 gpio6 gpio5 vdd0 vdda vgg tms hc05 hc02 hc06 hc04 hc03 em2_rxd1 em2_rxd2 em2_rxdv em2_rxer em2_rxd3 nc vss vdd vddo vddo em1_rxdv gpio25 had15 hc01 gpio26 em2_col em2_rx_clk vsso usbn ma05 vss vdd had31 (hcs4#)/gpio37 em1_mdc had13 em1_mdio vss0 em1_rxer mb0 vsso usb_pwr_det (gpio22) usbp mb1 vddo vsso md08 had11 had12 had07 had14 vddo vsso ma00 ma01 ma03 ma02 mm1 md02 md06 vddo had03 had06 had05 had08 had10 had09 ma04 vsso ma06 ma07 mm0 md00 md04 vsso md12 vddo had02 had04 vddo vsso vddo ma08 ma10 vsso mcke vddo md09 md14 em2_crs em2_txd1 em2_txd2 hc09 (hwr#) had01 had00 ma09 ma11 mcas# mras# md01 md05 md10 md13 em2_tx_en vsso em2_tx_clk hc08 (hrd#) vddo vsso em2_rxd0 mwe# mcs# vddo mclk md03 md07 md11 md15 em2_txer em2_txd3 em2_txd0 hrst# hc00 (hcs0#)/gpio32
cx82100 home network processor data sheet 2-4 conexant proprietary and confidential information 101306c table 2-1. cx82100-11/-12/-51/-52 hnp pin signals ? 196-pin fpbga pin signal pin signal pin signal pin signal a1 gpio24 d8 vsso h1 em1_rxd2 l8 had13 a2 gpio18 d9 usbp h2 em1_rxd3 l9 had07 a3 gpio17 d10 ma02 h3 em1_rxd1 l10 had05 a4 tst2 d11 ma07 h4 em1_rxd0 l11 had02 a5 vsso d12 vsso h5 vssa l12 em2_txd2 a6 em2_mdio d13 mras# h6 vgg l13 em2_tx_clk a7 em2_rxd1 d14 vddo h7 vdd l14 em2_txd3 a8 gpio26 e1 em1_tx_clk h8 vdd m1 had26 a9 mb0 e2 i2c_data (gpio15) h9 md08 m2 had27 a10 ma00 e3 i2c_clock (gpio16) h10 vddo m3 had23 a11 ma04 e4 em1_txd3 h11 vsso m4 had20 a12 vddo e5 gpio7 h12 md14 m5 had16 a13 ma09 e6 gpio5 h13 md13 m6 hc06 a14 em2_rxd0 e7 em2_rxd3 h14 md11 m7 gpio25 b1 gpio20 e8 usbn j1 fclkio/gpio39 m8 em1_mdio b2 gpio19 e9 mb1 j2 clki m9 had14 b3 vddo e10 mm1 j3 pllbp m10 had08 b4 tst1 e11 mm0 j4 trst# m11 had04 b5 vddo e12 mcke j5 bclkio/gpio38 m12 hc09 (hwr#) b6 em2_mdc e13 md01 j6 tms m13 hc08 (hrd#) b7 em2_rxd2 e14 mclk j7 vddo m14 em2_txd0 b8 em2_col f1 em1_tx_en j8 had31 (hcs4#)/gpio37 n1 had24 b9 vsso f2 em1_txd0 j9 had11 n2 had25 b10 ma01 f3 em1_txd2 j10 had03 n3 had22 b11 vsso f4 vsso j11 md12 n4 had19 b12 ma08 f5 em1_txd1 j12 em2_crs n5 vddo b13 ma11 f6 vddo j13 em2_tx_en n6 hc04 b14 mwe# f7 nc j14 md15 n7 had15 c1 nc f8 ma05 k1 tdi n8 vsso c2 nc f9 vddo k2 tck n9 vddo c3 gpio21 f10 md02 k3 tdo n10 had10 c4 vsso f11 md00 k4 bopt (gpio14) n11 vddo c5 tst0 f12 vddo k5 treqa n12 had01 c6 gpio31 f13 md05 k6 hc05 n13 vddo* c7 em2_rxdv f14 md03 k7 vddo n14 hrst# c8 em2_rx_clk g1 em1_col k8 em1_mdc p1 vddo c9 usb_pwr_det (gpio22) g2 em1_crs k9 had12 p2 vsso c10 ma03 g3 em1_txer k10 had06 p3 had21 c11 ma06 g4 gpio27 k11 vddo p4 had18 c12 ma10 g5 em1_rx_clk k12 em2_txd1 p5 vsso c13 mcas# g6 vdda k13 vsso p6 hc03 c14 mcs# g7 vss k14 em2_txer p7 hc01 d1 vddo g8 vss l1 had28 p8 em1_rxer d2 nc g9 vsso l2 vsso p9 vsso d3 nc g10 md06 l3 had29 p10 had09 d4 tst3 g11 md04 l4 had17 p11 vsso d5 gpio8 g12 md09 l5 hc07 p12 had00 d6 gpio6 g13 md10 l6 hc02 p13 vsso* d7 em2_rxer g14 md07 l7 em1_rxdv p14 hc00 (hcs0#)/gpio32* * different from cx82100-41/-41.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 2-5 figure 2-3. cx82100-41/-42 hnp hardware interface signals em1_col em1_crs em1_mdc em1_mdio em1_rx_clk em1_rxd0 em1_rxd1 em1_rxd2 em1_rxd3 em1_rxdv em1_rxer em1_tx_clk em1_tx_en em1_txd0 em1_txd1 em1_txd2 em1_txd3 em1_txer em2_col em2_crs em2_mdc em2_mdio em2_rx_clk em2_rxd0 em2_rxd1 em2_rxd2 em2_rxd3 em2_rxdv em2_rxer em2_tx_clk em2_tx_en em2_txd0 em2_txd1 em2_txd2 em2_txd3 em2_txer usbp usbn usb_pwr_det (gpio22)* clki hrst# vgg vdd vdda vddo vss vssa vsso tst0 tst1 tst2 tst3 pllbp bopt (gpio14)* treqa gpio5 gpio6 gpio7 gpio8 gpio17 gpio18 gpio19 gpio20 gpio21 gpio24 gpio25 gpio26 gpio27 gpio31 bclkio/gpio38 fclkio/gpio39 g1 g2 k8 m8 g5 h4 h3 h1 h2 l7 p8 e1 f1 f2 f5 f3 e4 g3 b8 j12 b6 a6 c8 a14 a7 b7 e7 c7 d7 l13 j13 m14 k12 l12 l14 k14 d9 e8 c9 j2 n14 h6 h7, h8 g6 a12, b3, b5, d1, d14, f6, f9, f12, h10, j7, k7, k11, n5, n9, n11, p1 g7, g8 h5 a5, b9, b11, c4, d8, d12, f4, g9, h11, k13, l2, n8, n13, p2, p5, p9, p11 c5 b4 a4 d4 j3 k4 k5 e6 d6 e5 d5 a3 a2 b2 b1 c3 a1 m7 a8 g4 c6 j5 j1 +3.3v had00 had01 had02 had03 had04 had05 had06 had07 had08 had09 had10 had11 had12 had13 had14 had15 hc01 hc02 hc03 hc04 hc05 hc06 hc07 had16 had17 had18 had19 had20 had21 had22 had23 had24 had25 had26 had27 had28 had29 hc08 (hrd#) hc09 (hwr#) hc10 (hrdy#) hc00 (hcs0#)/gpio32 had31 (hcs4#)/gpio37 md00 md01 md02 md03 md04 md05 md06 md07 md08 md09 md10 md11 md12 md13 md14 md15 ma00 ma01 ma02 ma03 ma04 ma05 ma06 ma07 ma08 ma09 ma10 ma11 mm0 mm1 mb0 mb1 mras# mcas# mw e# mcs# mclk mcke i2c_data (gpio15)** i2c_clock (gpio16)** trst# tck tms tdi tdo nc nc nc nc nc p12 n12 l11 j10 m11 l10 k10 l9 m10 p10 n10 j9 k9 l8 m9 n7 p7 l6 p6 n6 k6 m6 l5 m5 l4 p4 n4 m4 p3 n3 m3 n1 n2 m1 m2 l1 l3 m13 m12 p14 p13 j8 f11 e13 f10 f14 g11 f13 g10 g14 h9 g12 g13 h14 j11 h13 h12 j14 a10 b10 d10 c10 a11 f8 c11 d11 b12 a13 c12 b13 e11 e10 a9 e9 d13 c13 b14 c14 e14 e12 e2 e3 j4 k2 j6 k1 k3 c1 c2 d2 d3 f7 101306_072 cx82100 (-41/-42) home network processor (hnp) 196-pin fpbga sdram or sram media independent interface 1 (mii 1)/ 7-wire serial interface (7-ws1) clock reset circuit jtag +3.3v or +5v (clamp) +1.8v +1.8v (through filter) parallel expansion bus d00 d01 d02 d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 rd# we# cs0# (flash) d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 dqmh dqml ba0 ba1 ras# cas# we# cs# clke clk sda scl usb interface media independent interface 2 (mii 2)/ 7-wire serial interface (7-ws2) serial eeprom (optional) col crs mdc mdio rx_clk rxd0 rxd1 rxd2 rxd3 rxdv rxer tx_clk tx_en txd0 txd1 txd2 txd3 txer col crs mdc mdio rx_clk rxd0 rxd1 rxd2 rxd3 rxdv rxer tx_clk tx_en txd0 txd1 txd2 txd3 txer * dedicated gpio signal. ** may be assigned to different application use if not used for indicated function. nc 4.7k 4.7k application dependent nc
cx82100 home network processor data sheet 2-6 conexant proprietary and confidential information 101306c figure 2-4. cx82100-41/-42 hnp pin signals-196-pin fpbga a1 b1 c1 d1 e1 f1 g1 h1 j1 k1 l1 m1 n1 p1 12345678 91011121314 a2 b2 c2 d2 e2 f2 g2 h2 j2 k2 l2 m2 n2 p2 a3 b3 c3 d3 e3 f3 g3 h3 j3 k3 l3 m3 n3 p3 a4 b4 c4 d4 e4 f4 g4 h4 j4 k4 l4 m4 n4 p4 a5 b5 c5 d5 e5 f5 g5 h5 j5 k5 l5 m5 n5 p5 a6 b6 c6 d6 e6 f6 g6 h6 j6 k6 l6 m6 n6 p6 a7 b7 c7 d7 e7 f7 g7 h7 j7 k7 l7 m7 n7 p7 a10 b10 c10 d10 e10 f10 g10 h10 j10 k10 l10 m10 n10 p10 a8 b8 c8 d8 e8 f8 g8 h8 j8 k8 l8 m8 n8 p8 a9 b9 c9 d9 e9 f9 g9 h9 j9 k9 l9 m9 n9 p9 a11 b11 c11 d11 e11 f11 g11 h11 j11 k11 l11 m11 n11 p11 a12 b12 c12 d12 e12 f12 g12 h12 j12 k12 l12 m12 n12 p12 a13 b13 c13 d13 e13 f13 g13 h13 j13 k13 l13 m13 n13 p13 a14 b14 c14 d14 e14 f14 g14 h14 j14 k14 l14 m14 n14 p14 a b c d e f g h j k l m n p gpio24 gpio20 nc vddo em1_tx_clk em1_tx_en em1_col em1_rxd2 fclkio/gpio39 tdi had28 had26 had24 vddo gpio18 gpio19 nc nc i2c_data (gpio15) em1_txd0 em1_crs em1_rxd3 clki tck vsso had27 had25 vsso top view 101306_073 gpio17 vddo gpio21 nc gpio16 em1_txd2 em1_txer em1_rxd1 pllbp tdo had29 had23 had22 had21 tst2 tst1 vsso tst3 em1_txd3 vsso gpio27 em1_rxd0 trst# bopt (gpio14) had17 had20 had19 had18 vsso vddo tst0 gpio8 gpio7 em1_txd1 em1_rx_clk vssa bclkio/gpio38 treqa hc07 had16 vddo vsso em2_mdio em2_mdc gpio31 gpio6 gpio5 vdd0 vdda vgg tms hc05 hc02 hc06 hc04 hc03 em2_rxd1 em2_rxd2 em2_rxdv em2_rxer em2_rxd3 nc vss vdd vddo vddo em1_rxdv gpio25 had15 hc01 gpio26 em2_col em2_rx_clk vsso usbn ma05 vss vdd had31 (hcs4#)/gpio37 em1_mdc had13 em1_mdio vss0 em1_rxer mb0 vsso usb_pwr_det (gpio22) usbp mb1 vddo vsso md08 had11 had12 had07 had14 vddo vsso ma00 ma01 ma03 ma02 mm1 md02 md06 vddo had03 had06 had05 had08 had10 had09 ma04 vsso ma06 ma07 mm0 md00 md04 vsso md12 vddo had02 had04 vddo vsso vddo ma08 ma10 vsso mcke vddo md09 md14 em2_crs em2_txd1 em2_txd2 hc09 (hwr#) had01 had00 ma09 ma11 mcas# mras# md01 md05 md10 md13 em2_tx_en vsso em2_tx_clk hc08 (hrd#) vsso hc00 (hcs0#)/gpio32 em2_rxd0 mwe# mcs# vddo mclk md03 md07 md11 md15 em2_txer em2_txd3 em2_txd0 hrst# hc10 (hrdy#)
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 2-7 table 2-2. cx82100-41/-42 hnp pin signals ? 196-pin fpbga pin signal pin signal pin signal pin signal a1 gpio24 d8 vsso h1 em1_rxd2 l8 had13 a2 gpio18 d9 usbp h2 em1_rxd3 l9 had07 a3 gpio17 d10 ma02 h3 em1_rxd1 l10 had05 a4 tst2 d11 ma07 h4 em1_rxd0 l11 had02 a5 vsso d12 vsso h5 vssa l12 em2_txd2 a6 em2_mdio d13 mras# h6 vgg l13 em2_tx_clk a7 em2_rxd1 d14 vddo h7 vdd l14 em2_txd3 a8 gpio26 e1 em1_tx_clk h8 vdd m1 had26 a9 mb0 e2 i2c_data (gpio15) h9 md08 m2 had27 a10 ma00 e3 i2c_clock (gpio16) h10 vddo m3 had23 a11 ma04 e4 em1_txd3 h11 vsso m4 had20 a12 vddo e5 gpio7 h12 md14 m5 had16 a13 ma09 e6 gpio5 h13 md13 m6 hc06 a14 em2_rxd0 e7 em2_rxd3 h14 md11 m7 gpio25 b1 gpio20 e8 usbn j1 fclkio/gpio39 m8 em1_mdio b2 gpio19 e9 mb1 j2 clki m9 had14 b3 vddo e10 mm1 j3 pllbp m10 had08 b4 tst1 e11 mm0 j4 trst# m11 had04 b5 vddo e12 mcke j5 bclkio/gpio38 m12 hc09 (hwr#) b6 em2_mdc e13 md01 j6 tms m13 hc08 (hrd#) b7 em2_rxd2 e14 mclk j7 vddo m14 em2_txd0 b8 em2_col f1 em1_tx_en j8 had31 (hcs4#)/gpio37 n1 had24 b9 vsso f2 em1_txd0 j9 had11 n2 had25 b10 ma01 f3 em1_txd2 j10 had03 n3 had22 b11 vsso f4 vsso j11 md12 n4 had19 b12 ma08 f5 em1_txd1 j12 em2_crs n5 vddo b13 ma11 f6 vddo j13 em2_tx_en n6 hc04 b14 mwe# f7 nc j14 md15 n7 had15 c1 nc f8 ma05 k1 tdi n8 vsso c2 nc f9 vddo k2 tck n9 vddo c3 gpio21 f10 md02 k3 tdo n10 had10 c4 vsso f11 md00 k4 bopt (gpio14) n11 vddo c5 tst0 f12 vddo k5 treqa n12 had01 c6 gpio31 f13 md05 k6 hc05 n13 vsso* c7 em2_rxdv f14 md03 k7 vddo n14 hrst# c8 em2_rx_clk g1 em1_col k8 em1_mdc p1 vddo c9 usb_pwr_det (gpio22) g2 em1_crs k9 had12 p2 vsso c10 ma03 g3 em1_txer k10 had06 p3 had21 c11 ma06 g4 gpio27 k11 vddo p4 had18 c12 ma10 g5 em1_rx_clk k12 em2_txd1 p5 vsso c13 mcas# g6 vdda k13 vsso p6 hc03 c14 mcs# g7 vss k14 em2_txer p7 hc01 d1 vddo g8 vss l1 had28 p8 em1_rxer d2 nc g9 vsso l2 vsso p9 vsso d3 nc g10 md06 l3 had29 p10 had09 d4 tst3 g11 md04 l4 had17 p11 vsso d5 gpio8 g12 md09 l5 hc07 p12 had00 d6 gpio6 g13 md10 l6 hc02 p13 hc00 (hcs0#)/gpio32* d7 em2_rxer g14 md07 l7 em1_rxdv p14 hc10 (hrdy#) * different from cx82100-11/-12/-51/-52.
cx82100 home network processor data sheet 2-8 conexant proprietary and confidential information 101306c table 2-3. cx82100 hnp pin signal definitions pin signal pin no. i/o i/o type signal name/description power and ground vdd h7, h8 p pwr core supply voltage. connect to +1.8v. vdda g6 p pwr supply voltage. connect to +1.8v through filter. vddo a12, b3, b5, d1, d14, f6, f9, f12, h10, j7, k7, k11, n5, n9, n11, p1 ppwr i/o supply voltage. connect to +3.3v. vddo n13 (cx82100 -11/-12/-51/-52) ppwr i/o supply voltage. connect to +3.3v. vgg h6 r ref i/o clamp power supply. connect to +5v if available, otherwise connect to +3.3v. vss g7, g8 g gnd core ground. connect to digital ground. vssa h5 g gnd ground. connect to digital ground. vsso a5, b9, b11, c4, d8, d12, f4, g9, h11, k13, l2, n8, p2, p5, p9, p11 ggnd i/o ground. connect to digital ground. vsso n13 (cx82100 ?41/-42) ggnd i/o ground. connect to digital ground. vsso p13 (cx82100 -11/-12/-51/-52) ggnd i/o ground. connect to digital ground. system control hrst# n14 i ith reset. active low input asserted for at least 100 s to reset the hnp. all hardware registers are initialized to their default state. upon de-assertion of hrst#, the hnp executes the boot loader code (see bopt pin) then starts processing of the application code. connect hrst# to a reset circuit. bopt (gpio14) k4 i/o itpu/ot4 boot loader option. upon de-assertion of the hrst# signal, the boot loader code executes from internal rom (bopt pin high, i.e., open) or flash rom (bopt pin low, i.e., connected to gnd). for normal operation, typically connect bopt to gnd through 4.7 k ? to execute boot loader from flash rom. pllbp j3 i itpd pll bypass mode select. if the pllbp pin is high (test mode), pins fclkio and bclkio are fclkio and bclkio inputs only (i.e., not gpio pins). if the pllbp pin is low (normal operation), pins fclkio and bclkio operate as fclkio/gpio39 and bclkio/gpio38 as selected in the gpio_opt register). for normal operation, connect pllbp to gnd through 4.7 k ? . clock interface clki j2 i ith clock in. connect to 35.328 mhz voltage controlled crystal oscillator (vcxo) output through 51 ? . bclkio/gpio38 j5 i/o itpu/ot4 bit clock i/o. if pllbp pin is high (test mode), this pin is bclkio input only (i.e., not gpio38). if the pllbp pin is low (normal operation), this pin can be used as gpio38 or bclkio (see gpio_opt register bit 6 and pllbp pin). for normal operation, bclkio output supplies the 25 mhz to the lan1 and lan2 interfaces. connect bclkio to the lan 1 x1 pin and to the lan2 x1 pin though a single 51 ? resistor. fclkio/gpio39 j1 i/o itpu/ot4 frame clock i/o. if the pllbp pin is high (test mode), this pin is fclkio input only (i.e., not gpio39). if the pllbp pin is low (normal operation), this pin can be used as gpio39 or fclkio (see gpio_opt register bit 7 and pllbp pin).
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 2-9 table 2-3. cx82100 hnp pin signal definitions (continued) pin signal pin no. i/o i/o type signal name/description usb interface usbp usbn d9 e8 i/o iu/ou usb port . usbp and usbn are the differential data positive and negative signals of the usb port. connect usbp and usbn to usb +data and -data, respectively, through 24 ? , and optionally through a quick switch in order to isolate the usbp and usbn from the usb during suspend mode. usb_pwr_det (gpio22) c9 i it/ot4 usb power detect . active high input used to detect presence of +5 v at the usb connector. jtag interface trst# j4 i itpu jtag reset. a high-to-low transition on this signal forces the tap controller into a logic reset state. this pin has an internal pullup. leave open for normal operation. tck k2 i itpu jtag test clock. this is the boundary scan clock input signal. this pin has an internal pullup. leave open for normal operation. tms j6 i itpu jtag test mode select. this signal controls the operation of the tap controller. this pin has an internal pull-up. leave open for normal operation. tdi k1 i itpu jtag test input. this signal contains serial data that is shifted in on the rising edge of tck. the pin has an internal pullup. leave open for normal operation. tdo k3 o otts4 jtag test output data. this is the three-stateable boundary scan data output signal from the mcu, and it is shifted out on the falling edge of tck. leave open for normal operation. test interface controller (tic) [factory test only] treqa k5 i itpd reserved. this pin is connected to internal circuitry. leave open.
cx82100 home network processor data sheet 2-10 conexant proprietary and confidential information 101306c table 2-3. cx82100 hnp pin signal definitions (continued) pin signal pin no. i/o i/o type signal name/description emac 1 interface em1_col g1 i itpd lan 1 collision indication. in full-duplex mode, em1_col is ignored. in half-duplex mode, em1_col is asserted by the lan 1 ephy upon detection of a collision on the medium, and remains asserted while the collision condition persists. for mii, connect to lan 1 ephy col pin through 51 ? . for 7-ws interface, connect to lan 1 ephy col pin through 51 ? . em1_crs g2 i itpd lan 1 carrier sense. in full-duplex mode, em1_crs is ignored. in half-duplex mode, em1_crs is asserted by the lan 1 ephy when either the transmit or receive medium is not idle. it is de- asserted by the lan 1 ephy when both the transmit and receive media are idle. the lan 1 ephy ensures that em1_crs remains asserted throughout the duration of a collision condition, i.e., when em1_col = 1. for mii, connect to lan 1 ephy crs pin through 51 ? . for 7-ws interface, connect to lan 1 ephy crs pin through 51 ? . em1_mdc k8 o otts4 lan 1 management data clock. em1_mdc is sourced by the station management entity (sta) of the emac as the timing reference for transfer of information on the em1_mdio signal. em1_mdc is aperiodic and has no maximum high or low times. the minimum high and low time for em1_mdc is 160 ns each. the minimum period for em1_mdc is 400 ns. for mii, connect to lan 1 ephy col pin. for 7-ws interface, leave open (not used). em1_mdio m8 i/o itpd/ot4 lan 1 serial management data input/output. em1_mdio is a bidirectional signal used to transfer control and status information between the lan 1 ephy and the sta in the emac. for mii, connect to lan 1 ephy mdio pin and to +3.3v through 4.7 k ? . for 7-ws interface, connect to lan 1 ephy mdio pin and to +3.3v through 4.7 k ? . em1_rx_clk g5 i itpd lan 1 receive clock. a 10 mhz square wave synchronized to the receive data and only active while receiving an input bit stream. em1_rx_clk is sourced by the lan 1 ephy. it provides the timing reference for the transfer of em1_rxdv, em1_rxd[3:0], and em1_rxer signals from lan 1 ephy. the lan 1 ephy can either recover em1_rx_clk from the received data or it may derive em1_rx_clk from a nominal clock (e. g., the em1_tx_clk reference). if loss of received signal from the medium causes the lan 1 ephy to lose the recovered clock reference, the lan 1 ephy must source the clock from a nominal clock reference. transitions from nominal clock to recovered clock or vice versa are made only when em1_rxdv is de-asserted. during the interval between the assertion of em1_crs and the assertion of em1_rxdv at the beginning of a frame, the lan 1 ephy may extend a cycle of em1_rx_clk by holding it either high or low until the lan 1 ephy has locked to the recovered clock. following the de-assertion of em1_rxdv at the end of a frame, the lan 1 ephy may extend a cycle of em1_rx_clk by holding it either high or low for an interval not to exceed twice the nominal clock period. for mii, connect to lan 1 ephy rx_clk pin 51 ? . for 7-ws interface, connect to lan 1 ephy rx_clk pin 51 ? .
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 2-11 table 2-3. cx82100 hnp pin signal definitions (continued) pin signal pin no. i/o i/o type signal name/description em1_rxd[3:0] h2, h1, h3, h4 i itpd lan 1 receive data. for mii interface, em1_rxd[3:0] are the 4- bit parallel receive data lines. connect em1_rxd[3:0] to lan 1 phy rxd[3:0] through 51 ? . for 7-ws interface, em1_rxd3 is the receive input bit stream. connect em1_rxd3 to lan 1 ephy rxd pin through 51 ? . em1_rxd[2:0] are not used and should be left open. em1_rxdv l7 i itpd lan 1 receive data valid. em1_rxdv is asserted by the lan 1 ephy to indicate that the nibble on em1_rxd[3:0] is valid. it remains asserted for the received frame duration with the exception of the preamble. it may or may not be asserted during the preamble. em1_rxdv is de-asserted prior to the first em1_rx_clk period that follows the final nibble of a received frame. when em1_rxdv is de-asserted, the emac ignores em1_rxd[3:0]. for mii, connect to lan 1 ephy rx_dv pin through 51 ? . for 7-ws interface, leave open (not used). em1_rxer p8 i itpd lan 1 receive error. em1_rxer is driven by the lan 1 ephy. it is asserted for one or more em1_rx_clk periods to indicate that an error was detected somewhere in the frame presently being transferred from the lan 1 ephy. the rmac hardware will detect this condition and declare such a frame invalid. while em1_rxdv is deasserted, em1_rxer has no effect on the reconciliation sublayer (which lies between the mii and the mac), therefore, it has no effect on the mac as well. for mii, connect to lan 1 ephy rx_rxer pin through 51 ? . for 7-ws interface, leave open (not used). em1_tx_clk e1 i itpd transmit clock. em1_tx_clk is sourced by the lan 1 ephy. it provides the timing reference for the transfer of em1_tx_en, em1_txd[3:0], and em1_txer signals to lan 1 ephy. for mii, connect to lan 1 ephy tx_clk pin through 51 ? . for 7-ws interface, connect to lan phy tx_clk pin through 51 ? . em1_tx_en f1 o otts4 lan 1 transmit enable. em1_tx_en is driven off the rising edge and sampled on the rising edge of em1_tx_clk. it indicates that the hnp is presenting nibbles on the mii for transmission. em1_tx_en is asserted when the hnp has data to transmit over the medium and remains asserted for the duration of the entire transmitted frame. the hnp de-asserts em1_tx_en prior to the rising edge of em1_tx_clk following the final nibble of a frame. for mii, connect to lan 1 ephy tx_en pin. for 7-ws interface, connect to lan 1 ephy tx_en pin. em1_txd[3:0] e4, f3, f5, f2 o otts4 lan 1 transmit data. for mii interface, em1_txd[3:0] are the 4- bit parallel transmit data lines. em1_txd[3:0] is driven off the rising edge and sampled on the rising edge of em1_tx_clk. the entire transmitted frame data is presented by the em1_txd[3:0] signal lines, and commences on the first leading edge of em1_tx_clk subsequent to em1_tx_en assertion. for each em1_tx_clk period in which em1_tx_en is asserted, em1_txd[3:0] are accepted for transmission by the lan 1 ephy. all fields except for the fcs are transmitted with the least significant nibble first. the lsb of each nibble is placed on em1_txd0. connect em1_txd[3:0] to lan 1 ephy txd[3:0] through 51 ? . for 7-ws interface, em1_txd3 is the transmit input bit stream. connect em1_txd3 to lan 1 ephy txd pin. em1_txd[2:0] are not used and should be left open.
cx82100 home network processor data sheet 2-12 conexant proprietary and confidential information 101306c table 2-3. cx82100 hnp pin signal definitions (continued) pin signal pin no. i/o i/o type signal name/description em1_txer g3 o otts4 lan 1 transmit coding error. when em1_txer is asserted for one or more em1_tx_clk periods while em1_tx_en is also asserted, the lan 1 ephy emits one or more symbols that are not part of the valid data or delimiter set somewhere in the frame being transmitted. permissible encoding of em1_txer with em1_tx_en and em1_txd[3:0] are: em1_tx_en em1_txer em1_txd[3:0] description 0 0 0000?1111 normal inter-frame 0 1 0000?1111 reserved 1 0 0000?1111 normal data transmission 1 1 0000?1111 transmit error propagation for mii, connect to lan 1 ephy txer pin. for 7-ws interface, leave open. emac 2 interface the emac 2 interface is the same as the emac 1 interface. refer to the emac1 interface for signal definitions. em2_col b8 i itpd lan 2 collision indication. em2_crs j12 i itpd lan 2 carrier sense. em2_mdc b6 o otts4 lan 2 management data clock. em2_mdio a6 i/o itpd/ot4 lan 2 serial management data input/output. em2_rx_clk c8 i itpd lan 2 receive clock. em2_rxd[3:0] e7, b7, a7, a14 iitpd lan 2 receive data. em2_rxdv c7 i itpd lan 2 receive data valid. em2_rxer d7 i itpd lan 2 receive error em2_tx_clk l13 i itpd lan 2 transmit clock. em2_tx_en j13 o otts4 lan 2 transmit enable . em2_txd[3:0] l14, l12, k12, m14 ootts4 lan 2 transmit data. em2_txer k14 o otts4 lan 2 transmit error.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 2-13 table 2-3. cx82100 hnp pin signal definitions (continued) pin signal pin no. i/o i/o type signal name/description host parallel expansion bus interface had[15:0] n7, m9, l8, k9, j9, n10, p10, m10, l9, k10, l10, m11, j10, l11, n12, p12 i/o itpu/ot4 data lines 15-00. typically, connect to flash rom d[15:0], respectively. had[29:16] l3, l1, m2, m1, n2, n1, m3, n3, p3, m4, n4, p4, l4, m5 oit/ot4 address lines 20-7. typically, connect to flash rom a[20:10], respectively. hc[07:01] l5, m6, k6, n6, p6, l6, p7 oit/ot4 address lines 6-0. typically, connect to flash rom a[6:0], respectively. hc08 (hrd#) m13 o it/ot4 read enable. active low read enable asserted when data is transferred from the selected device onto the data bus. typically, connect through 51 ? as hrd# to flash rom oe# and through 51 ? as hrdua# to uart oe#. hc09 (hwr#) m12 o it/ot4 write enable. active low write enable asserted when data is transferred from the data bus into the selected device. typically, connect through 51 ? as hwr# to flash rom wr# and through 51 ? as hwrua# to uart wr#. hc00 (hcs0#)/ gpio32 p14 (cx82100 -11/-12/-51/-51) p13 (cx82100 -41/-42) oit/ot4 flash rom chip enable. active low output enables optional flash rom when asserted. connect to flash rom ce#. hc10 (hrdy#) p14 (cx82100 -41/-42) i itpd/ot4 application dependent. had31 (hcs4#)/ gpio37 j8 o it/ot4 application dependent. serial eeprom interface i2c_data (gpio15) e2 i/o itpu/ot4 serial eeprom data. i2c_data is a bidirectional data line used to transfer data into and out of the eeprom. connect to the eeprom sda pin and to +3.3v through 4.7k ? . i2c_clock (gpio16) e3 o itpu/ot4 serial eeprom shift clock . the i2c_clock output is used to clock all data into and out of the eeprom. connect to the eeprom scl pin and to +3.3v through 4.7k ? .
cx82100 home network processor data sheet 2-14 conexant proprietary and confidential information 101306c table 2-3. cx82100 hnp pin signal definitions (continued) pin signal pin no. i/o i/o type signal name/description sdram/sram interface ma[11:00] b13, c12, a13, b12, d11, c11, f8, a11, c10, d10, b10, a10 oot4 sdram/sram address lines. twelve-bit multiplexed row and column address bus addresses up to 8 mb of data. connect to sdram/sram a[11:0], respectively, through 51 ? . md[15:00] j14, h12, h13, j11, h14, g13, g12, h9, g14, g10, f13, g11, f14, f10, e13, f11 i/o itpu/ot4 sdram/sram data lines. sixteen-bit bidirectional data bus. connect to sdram/sram d[15:0], respectively, through 51 ? . mm0 e11 o ot4 sdram input/output mask 0/sram a12. for sdram interface, this signal is a mask for write access. connect to sdram i/o mask low input through 51 ? . for sram interface, this signal is address a12 output, connect to sram a12 input through 51 ? . mm1 e10 o ot4 sdram input/output mask 1/sram a13. for sdram interface, this signal is a mask for write access. connect to sdram i/o mask high input through 51 ? . for sram interface, this signal is address a13 output. connect to sram a13 input through 51 ? . mb0 a9 o ot4 sdram bank address select 0/sram a14. for sdram interface, this signal selects the active bank. connect to sdram/sram bank address select 0 input through 51 ? for 8 mb sdram; leave open for 2 mb sdram. for sram interface, this signal is address a14 output. connect to sram a14 input through 51 ? . mb1 e9 o ot4 sdram bank address select 1/sram a15. for sdram interface, this signal selects the active bank. connect to sdram/sram bank address select 1 input through 51 ? . for sram interface, this signal is address a15 output. connect to sram a15 input through 51 ? . mcs# c14 o ot4 sdram memory chip select/sram 2 chip enable. for sdram interface, this active low output enables the sdram command decoder. connect to sdram cs# input through 51 ? . for sram interface, this active low output enables sram 2. if one sram is used, leave open; if two srams are used, connect to sram 2 ce# input through 51 ? . mras# d13 o ot4 sdram row address strobe/sram 1 chip enable. for sdram interface, this active low output starts sdram access with strobe of row address. connect to sdram ras# input through 51 ? . for sram interface, this active low output enables sram 1. if one sram is used, connect to sram ce# input; if two srams are used, connect to sram 1 ce# input through 51 ? . mcas# c13 o ot4 sdram column address strobe/sram a16. for sdram interface, this active low output strobes column address and data bytes. connect to sdram cas# input through 51 ? . for sram interface, this signal is address a16 output. connect to sram a16 input through 51 ? .
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 2-15 table 2-3. cx82100 hnp pin signal definitions (continued) pin signal pin no. i/o i/o type signal name/description sdram/sram interface (continued) mwe# b14 o ot4 sdram/sram memory write enable. this active low output enables write access to sdram/sram. connect to sdram/sram we# input through 51 ? . mcke e12 o ot4 sdram clock enable/sram a17. for sdram interface, this active high output enables the sdram clock. connect to sdram clke input through 51 ? . for sram interface, this signal is address a17 output. connect to sram a17 input through 51 ? . mclk e14 o ot4 sdram clock. for sdram interface, this signal supplies the clock to the sdram. connect to sdram clk input through 51 ? . all sdram signals are sampled on the positive (rising) edge. for sram interface, this pin not used. leave open. general purpose input/output (gpio) recommended gpio usage is listed in table 2-9. gpio31 c6 i/o itpu/ot4 application dependent. reset state = z(pu). gpio27 g4 i/o itpu/ot4 application dependent. reset state = z(pu). gpio26 a8 i/o itpu/ot4 application dependent. reset state = z(pu). gpio24 a1 i/o itpu/ot4 application dependent. reset state = z(pu). gpio21 c3 i/o itpu/ot4 application dependent. reset state = z(pu). gpio20 b1 i/o itpu/ot4 application dependent. reset state = z(pu). gpio19 b2 i/o itpu/ot4 application dependent. reset state = z(pu). gpio18 a2 i/o itpu/ot4 application dependent. reset state = z(pu). gpio17 a3 i/o itpu/ot4 application dependent. reset state = low. gpio8 d5 i/o itpu/ot4 application dependent. reset state = low. gpio7 e5 o itpu/ot4 application dependent. reset state = z(pu). gpio6 d6 o itpu/ot4 application dependent. reset state = z(pu). gpio5 e6 o itpu/ot4 application dependent. reset state = z(pu). test tst[3:0] d4, a4, b4, c5 test pins. test configuration pins used only during the manufacturing/test process. for normal operation, connect tst[3:0] to ground. no connect pins (balls) nc c1, c2, d2, d3, f7 no connect. these pins (solder balls) are not connected to internal circuitry. leave open. notes: 1. i/o types: see table 2-4. 2. unless otherwise specified, output pins or input pins with internal pulldowns or pullups can be left open if not used. 3. the reset state notation indicates the state of the pin upon power-on and whether or not it has an internal pullup. z means a high impedance state (an input) and pu/pd means the pin has an internal pullup/pulldown.
cx82100 home network processor data sheet 2-16 conexant proprietary and confidential information 101306c table 2-4. cx82100 hnp input/output type descriptions i/o type description it digital input, +5v tolerant, c in = 8 pf it/ot4 digital input, +5v tolerant, c in = 8 pf/digital output, 4 ma, z int = 80 ? ith digital input, +5v tolerant, with hysteresis, c in = 8 pf ithpd digital input, +5v tolerant, with hysteresis, 75k ? pull-down, c in = 8 pf itpd digital input, +5v tolerant, 75k ? pull-down, c in = 8 pf itpu digital input, +5v tolerant, 75k ? pull-up, c in = 8 pf itpu/ot4 digital input, +5v tolerant, 75k ? pull-up, c in = 8 pf/digital output, 4 ma, z int = 80 ? otts4 digital output, 3-state, 4 ma, z int =80 ? iu/ou input, usb receiver/output, usb driver notes: see dc characteristics in table 2-5. i/o type corresponds to the device pad type. the i/o column in tables refers to signal i/o direction used in the application.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 2-17 2.2 cx82100 hnp electrical and environmental specifications 2.2.1 dc electrical characteristics cx82100 hnp dc electrical characteristics are listed in table 2-5. table 2-5. cx82100 hnp dc electrical characteristics parameter symbol min. typ. max. units test conditions 1 input high voltage vih 2.0 vgg + 0.5 vdc input low voltage vil -0.5 0.8 vdc input leakage current iil/iih a vin = 0 for min. vin = vin (max) for max. input leakage current (with internal pull- downs) 2 iil/iih a vin = 0 for min. vin = vin (max) for max. input leakage current (with internal pull- ups) 2 iil/iih a vin = 0 for min. vin = vin (max) for max. internal pullup/pulldown resistance rpu/rpd 50 200 k ? output high voltage voh 2.4 vddo vdc ioh = 4 ma output low voltage vol 0.4 vdc iol = 4 ma input/output capacitance cinout 3 pf notes: 1. test conditions (unless otherwise stated): vddcore = +1.8 0.15 vdc vddo = +3.3 0.3 vdc; v in (max) = +3.6v for vgg connected to +3.3v; v in (max) = +5.25v for vgg connected to +5v. 2. current flow out of the device is shown as minus. 3. stresses above those listed may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods of time may affect device reliability.
cx82100 home network processor data sheet 2-18 conexant proprietary and confidential information 101306c 2.2.2 operating conditions, absolute maximum ratings, and power consumption cx82100 hnp operating conditions are specified in table 2-6. cx82100 hnp absolute maximum ratings are stated in table 2-7. cx82100 hnp power consumption is listed in table 2-8. table 2-6. cx82100 hnp operating conditions parameter symbol min typ max units core circuits supply voltage vdd 1.65 1.8 1.95 vdc i/o circuits supply voltage vddo 3.0 3.3 3.6 vdc i/o clamp voltage vgg* vdc operating ambient temperature t a 070 c *connect vgg to the highest signaling level being used to drive input signals, i.e. +3.3 v or +5 v. table 2-7. cx82100 hnp absolute maximum ratings parameter symbol min max units core circuits supply voltage vdd -0.35 2.0 vdc i/o circuits supply voltage vddo -0.35 3.7 vdc input voltage v in -0.35 vgg + 0.35* vdc voltage applied to outputs in high impedance (off) state v hz -0.35 vgg + 0.35* vdc storage temperature t s -55 125 c * vgg = +3.3 v 0.3 v or +5 v 0.25 v. caution: handling cmos devices these devices contain circuitry to protect the inputs against damage due to high static voltages. however, normal precautions should be taken to avoid application of any voltage higher than maximum rated voltage. an unterminated input can acquire unpredictable voltages through coupling with stray capacitance and internal crosstalk. both power dissipation and device noise immunity degrades. therefore, all inputs should be connected to an appropriate supply voltage. input signals should never exceed the voltage range from 0.5v or more negative than gnd to 0.5v or more positive than vdd. this prevents forward biasing the input protection diodes and possibly entering a latch up mode due to high current transients. table 2-8. cx82100 hnp power consumption supply voltage typical current (ma) maximum current (ma) typical power (mw) maximum power (mw) vdd 85 105 155 205 vddo 15 25 45 90 test conditions: vdd = +1.8 vdc for typical values; vdd = +1.95 vdc for maximum values. vddo = +3.3 vdc for typical values; vddo = +3.6 vdc for maximum values.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 2-19 2.3 optional gpio and host signal usage optional gpio and host signal usage is listed in table 2-9. recommended gpio signals are described in table 2-10. table 2-9. cx82100 hnp recommended gpio and host signal use pin name pin default use recommended use signal label reset state notes fclkio/gpio39 j1 gpio39 z(pu) bclkio/gpio38 j5 gpio38 z(pu) had31 (hcs4#)/gpio37 j8 had31 (hcs4#) hcs4#: high 5 hc00 (hcs0#)/gpio32 p14 hc00 (hcs0#) hcs0#: flash rom ce# high 2, 5 gpio31 c6 ? z(pu) 3 gpio27 g4 ? z(pu) 3 gpio26 a8 ? z(pu) 3 gpio25 m7 ? z(pu) 3 gpio24 a1 ? z(pu) 3 usb_pwr_det (gpio22) c9 ? usb power detect usb_pwr_det z 2, 6 gpio21 c3 ? z(pu) 3 gpio20 b1 ? lan 1 reset lan1_rst# z(pu) 3 gpio19 b2 ? z(pu) 3 gpio18 a2 ? z(pu) 3 gpio17 a3 ? low 3, 5 i2c_clock (gpio16) e3 ? serial eeprom shift clock i2c_clock z(pu) 2 i2c_data (gpio15) e2 ? serial eeprom data i2c_data z(pu) 2 bopt (gpio14) k4 ? boot loader option bopt z(pu) 2 gpio8 d5 ? low 3, 5 gpio7 e5 ? ready indicator led_ready z(pu) 3 gpio6 d6 ? lan 2 reset lan2_rst# z(pu) 3 gpio5 e6 ? z(pu) 3 notes: 1. refer to applicable reference design information for exact gpio use. 2. recommended system use. see table 2-2 for signal definition. 3. recommended application use. see table 2-4 for signal definition. 4. the reset state column indicates the state of the pin upon power-on and whether or not it has an internal pullup. z means a high impedance state (an input) and pu/pd means the pin has an internal pullup/pulldown. 5. gpios that default to chip selects (gpio32 and gpio37), as well as gpio8 and gpio17, default to output upon power-on. 6. gpio22 is the only gpio that does not have an internal pullup/down, so if usb detect is important or used, gpio22 should be assigned to it. if gpio22 is not used, or the firmware does not configure it to an output upon initialization, an external pullup/down must be implemented on the board.
cx82100 home network processor data sheet 2-20 conexant proprietary and confidential information 101306c table 2-10. cx82100 hnp definitions of recommended gpio and host signals pin signal pin no. i/o i/o type signal name/description led indicator interface led_ready (gpio7) e5 o itpu/ot4 ready indicator. active high output indicating the hnp is ready. connect led_ready (gpio7) to the led plus terminal. connect the led minus terminal to +3.3v through 100 ? . lan 1 interface lan1_rst# (gpio20) b1 o itpu/ot4 lan 1 reset. active low reset asserted to reset the lan 1 ephy. connect to lan 1 ephy rstb pin through 1 k ? . also, connect the lan 1 ephy rstb pin to +3.3v through 10 k ? and to gnd through 0.1 f. lan 2 interface lan2_rst# (gpio6) d6 o itpu/ot4 lan 2 reset. active low output asserted to reset the lan 2 ephy. connect to lan 2 ephy rstb pin through 1 k ? . also, connect the lan 2 ephy rstb pin to +3.3v through 10 k ? and to gnd through 0.1 f.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 2-21 2.4 interface timing and waveforms 2.4.1 external memory interface (sdram) the external memory interface provides a pc100-compatible sdram interface. signal interface timing is summarized in figure 2-5. note that mclk is derived from the bclk pll output (see section 12). accordingly, there is no fixed relationship between the hnp clock input (clki pin) and the external memory interface signals. figure 2-5. external memory interface timing 10 ns min. 1 ns min. 7.5 ns max. 4 ns min. 1 ns min. mclk mcke, ma[11:0] mb[1:0], mm[1:0], mcas#, mras#, mwe# md[15:0] (to sdram) md[15:0] (from sdram) 101545_072 2.4.2 host interface timing the signal interface timing for the host interface is user programmable. by programming the registers associated with the host interface, desired timing characteristics such as read/write pulse widths and setup and hold times can be established. for details regarding host interface timing, refer to section 5.1.5. 2.4.3 emac interface timing to be added. 2.4.4 usb interface timing to be added. 2.4.5 gpio interface timing the gpio outputs are derived from the bclk pll output (see clocking chapter). accordingly, there is no fixed relationship between the hnp?s clock input (clki) and the gpio signals.
cx82100 home network processor data sheet 2-22 conexant proprietary and confidential information 101306c 2.4.6 interrupt timing to be added. 2.4.7 clock reset timing to be added. 2.4.8 reset timing to be added.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 2-23 2.5 package dimensions the package dimensions for the 196-pin 15 mm x 15 mm fpbga are shown in figure 2-6. figure 2-6. package dimensions ? 196-pin 15 mm x 15 mm fpbga d1 e1 14 13 12 11 10 987 6 543 21 a b c d e f g h j k m n p l e e b bottom view top view side view a1 c a a2 d e pd_gp00-d608-001 a a1 a2 d d1 e e1 m n e b c coplanarity warpage min. 0.31 0.65 0.29 max. 1.50 0.41 0.75 0.39 0.12 0.10 15.00 ref 13.00 ref 15.00 ref 13.00 ref 1.00 ref 0.46 ref 14 min. 0.012 0.026 0.011 0.591 ref 0.512 ref 0.591 ref 0.521 ref 0.031 ref 0.018 ref max. 0.059 0.016 0.030 0.015 0.005 0.004 196 millimeters inches* dimension ref: gp00-d608-001 * dimensions in inches are for reference only; use metric dimensions for board design.
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cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 3-1 3 hnp memory architecture 3.1 hnp memory map the hnp system memory map is shown in figure 3-1. all internal and external memory and apb peripheral registers are memory-mapped directly to the first 16 mb region of the asb 32-bit address space. note that the map shows only the memory range reserved for each asb slave. the actual memory size required by each slave varies depending on its design. each memory area is allocated with a fixed starting address (i.e., it is not relocatable). from the figure, it can be seen that there are two different memory maps, run-time and boot-time. the reason for the different maps is to allow the operating system (os) to change the arm exception vectors located at address 0x0 at run-time. once boot is complete and memory maps are switched (external flash rom and internal ram address space is swapped), the os may change these exception vectors since they are now located in ram.
cx82100 home network processor data sheet 3-2 conexant proprietary and confidential information 101306c figure 3-1. hnp memory map 101545_007 run-time memory map 0x00000000 0x00180000 0x001fffff 0x00200000 0x002fffff 0x00300000 0x000fffff 0x00100000 0x0017ffff 0x003fffff 0x00400000 0x007fffff 0x00800000 0x00ffffff 0x01000000 reserved (512 kb) 0x0007ffff 0x00080000 16 mb space 0xffffffff 0x80000000 reserved (512 kb) reserved for internal ram expansion (480 kb) internal ram (32 kb) arm vector table (32 bytes) host master mode interface (1 mb) asb-to-apb bridge/dmac and apb peripherals (1 mb) external flash (4 mb) external sdram/sram (8 mb) reserved (4 gb - 16 mb) reserved (4 gb - 16 mb) (continued) reserved for internal rom expansion (448 kb) internal rom (64 kb) arm vector table (32 bytes) internal boot rom/ external flash rom (1 mb) internal ram (512 kb) reserved (512 kb) host master mode interface (1 mb) asb-to-apb bridge/dmac and apb peripherals (1 mb) external flash (4 mb) external sdram/sram (8 mb) reserved (4 gb - 16 mb) reserved (4 gb - 16 mb) (continued) boot-time memory map tic access
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 3-3 3.2 starting addresses the starting addresses for mapping asb and apb slaves are defined in table 3-1 and table 3-2, respectively. table 3-1. starting addresses for mapping asb slaves asb address: ba[31:0] asb slave description 0x000xxxxx external flash rom/internal ram 16k x 32 internal rom/external flash rom (boot-time); 8k x 32 internal ram (run-time) 0x0018xxxx internal ram/internal rom 8k x 32 internal ram (boot-time); 16k x 32 internal rom (run-time) 0x002xxxxx host interface host master mode peripherals interface 0x003xxxxx asb-to-apb bridge/dmac to asb-to-apb bridge and apb peripherals ? dword (4 bytes) access only 0x00400000? 0x007fffff external flash rom host master mode interface to 4 mb flash 0x00800000 - 0x00ffffff external sdram external sdram/sram interface to 8 mb sdram or up to 1 mb sram 0x80000000 arm940t arm940t tic access table 3-2. starting addresses for mapping apb slaves asb address: ba[31:0] apb slave description 0x0030xxxx asb-to-apb bridge/dmac asb-to-apb bridge slave and dmac 0x0031xxxx emac 1 ethernet media access control 1 0x0032xxxx emac 2 ethernet media access control 2 0x0033xxxx usb interface usb device controller 0x0034xxxx reserved 0x0035xxxx interrupts, timers, gpio, clock (itgc) miscellaneous peripherals (interrupts, timers, gpios, and clock) 3.2.1 arm vector table table 3-3 shows the exception vector addresses required by the arm940t. the first 32- byte space of the asb address space is reserved for this table. table 3-3. arm exception vector addresses address exception mode on entry 0x00000000 reset supervisor 0x00000004 undefined instruction undefined 0x00000008 software interrupt supervisor 0x0000000c abort (prefetch) abort 0x00000010 abort (data) abort 0x00000014 reserved reserved 0x00000018 irq# irq# 0x0000001c fiq# fiq#
cx82100 home network processor data sheet 3-4 conexant proprietary and confidential information 101306c 3.3 endianness the internal bus architecture supports only little-endian mode addressing (see figure 3-2). support for big-endian mode may occur in a peripheral that handles its data stream or in the host interface which may exchange data with a big-endian mode external processor. figure 3-2. little-endian mode addressing 100878-008 31:24 7:0 15:8 23:16 data bus byte lane no. 0 2 31 ba[1:0]=3 ba[1:0]=0 ba[1:0]=1 ba[1:0]=2 3.4 boot procedure there are two different scenarios for the boot procedure depending on the state of the bopt (gpio14) pin. upon power-on or reset, boot code will execute from internal rom if the bopt (gpio14) pin is high or from external flash rom if the bopt (gpio14) pin is low. when booting from internal rom, the boot code reads eeprom information (if an eeprom is installed) to set up the usb configuration of the hnp. once complete, usb communication between pc and the hnp can occur. when booting from external flash rom, the hnp maps the first mb of external flash rom space to internal rom space (see memory map in figure 3-1 for detailed information). a typical boot procedure begins by copying the flash boot code to internal ram. the run_map bit is set in the host control register (see 5.3.1) which causes the boot code to begin execution from internal ram. the boot code then configures the clocks and the enables the sdram. this enables the boot code to begin execution from internal ram. the boot code then copies the application firmware residing in flash to sdram. the boot code then jumps to the start of the application firmware in sdram. figure 3-3 illustrates the boot procedure.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 3-5 figure 3-3. boot procedure power-on-reset begin execution of the rom code. read signature bytes (first 4 bytes) of eeprom. is the signature present? read from eeprom, device descriptor, device config., endpoint config., lang. string id, manuf. string id, prod. string id, and store in sram. load udc, epinfo, endptbufs, configbufs, stringbufs, with sram data. continuous loop waiting for usb traffic. read from internal rom, device descriptor, device config., endpoint config., lang. string id, manuf. string id, prod. string id, and store in sram. y n power-on-reset begin execution of flash mapped to rom address space. flash boot code copies itself into sram. set run-map bit to swap rom and ram address space. now executing out of sram. enable sdram. set up fclk and blck frequencies. copy application firmware from flash to sdram. jump to start of application firmware in sdram and execute. gpio14 boot option pin flash boot(gpio14=0) internal rom boot(gpio14=1) typical flash boot scenario. 101545_009
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cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 4-1 4 dmac interface description the dma controller (dmac) is both an asb master and an apb master. it is integrated with the asb-to-apb bridge. using burst transfers and pipelining the data within the bus bridge interface optimizes asb efficiency. the dmac always performs qword (8 bytes) data transfers which require data valid on the entire 64-bit apb data bus. burst transfer on apb is not supported, however, data can be transferred on consecutive apb cycles (pclk cycles) for either read or write. 4.1 dma channel definition the dmac supports the data stream channels defined in table 4-1. each channel?s data- flow is considered with respect to the system memory?s point-of-view. a source channel has the memory supplying data to the dmac and on to the transmitter's output port. a destination channel is one where the memory receives data through the dmac from the receiver's input port. table 4-1. dma channel definition for dmac dma channel no. channel type channel description dma mode 1 src/dst emac1-txd lnk lst ? restart 2 dst emac1-rxd circ bfr ? restart 3 src/dst emac2-txd lnk lst ? restart 4 dst emac2-rxd circ bfr ? restart 5 src reserved 6 dst reserved 7 src m2m in src 8 dst m2m out dst 9 src usb-txd_ep3 lnk lst 10 src usb-txd_ep2 lnk lst 11 src usb-txd_ep1 lnk lst 12 dst usb-rxd circ bfr ? restart 13 src usb-txd_ep0 lnk lst 4.2 dma requests and data transfer the apb peripherals issue dma data transfer requests to the dmac. the knowledge of how much data will be received or transmitted resides within the peripheral. the physical interface transfers can be controlled to bit transfer resolution even though the dmac only operates at qword resolution. so the size of the packets actually dmaed (which may differ from that transmitted or received) is under peripheral control. the dmac just generates sequential incrementing addresses. table 4-2 lists all the request commands supported by dmac. dma action requests are signaled by encoding x{x}r where {x} represents the channel number. the signal x{x}r should remain idle except when issuing a specific request to the dmac. each event is signaled during a single pclk clock cycle. it is acceptable to have an interrupt or abort event directly follow a data transfer request. when an apb data
cx82100 home network processor data sheet 4-2 conexant proprietary and confidential information 101306c peripheral makes a dma data transfer request, however, it should not make another until after the current request has been processed (apb read or write). it is left up to the requestor (not the dmac) to log any overflow or underflow conditions. table 4-2. dma requests for apb peripherals x{x}r request dmac action 3?b000 dma_idle none 3?b001 dma_intr data pkt done interrupt forwarded to interrupt controller. 3?b010 dma_save save channel?s state (cnt and/or ptr). 3?b011 dma_reld reload or restore channel?s state from previous save. 3?b100 dma_xnxt data transfer request @ current pointer. ptr1+ = 8 (1 qword), cnt1-- (cnt1 represents the number of qwords) 3?b101 dma_xsav data transfer request @ saved pointer. ptr2+ = 8 (1 qword), cnt2-- (cnt2 represents the number of qwords) 3?b110 dma_xnul advance current pointer, skip data transfer. ptr1+ = 8 (1 qword), cnt1-- (cnt1 represents the number of qwords) 3?b111 reserved note that dma_xnxt and dma_xsav are the only dma commands that cause a data transfer. once issued, the channel requestor should not issue another until after their apb dma port has been accessed. the apb dma port qword read or write serves as the dmac acknowledge to the channel requestor. the actions dma_save, dma_reld, and dma_xnul should not be issued during a pending data transfer request since the current pointer and counter are not updated until the channel is serviced. usually dma_save will be issued just after the packet?s last qword transfer acknowledge. usually dma_reld is issued when a channel decides to abort a packet. dma_xnul is typically issued before starting a packet transfer. the action dma_xnul can be issued on consecutive pclks if the channel desires to move up its current pointer by several qwords. this action may not be issued when the dmac_{x}_cnt1 is equal to 1. dma_xnul may not be used just before an address link. normally, when dma_xnxt is issued for the last data qword, both the link and data transfers are scheduled concurrently, with the link transfer actually occurring first. two problems arise if dma_xnul is allowed to decrement the qword counter quickly. first, the address is changed before a link transfer can be scheduled into the dmac transfer queue with the correct address. second, there is nothing to prevent the requesting channel from issuing a dma_xnxt before the new address link is updated. 4.3 control registers per each dma channel {x}, the dmac can support three basic modes of address generation using up to two 22-bit dword- (4 bytes) aligned address pointers (dmac_{x}_ptr1, dmac_{x}_ptr2) and/or up to three 11-bit qword (8 bytes) counters (dmac_{x}_cnt1, dmac_{x}_cnt2, dmac_{x}_cnt3). dmac_{x}_ptr1 will always be readable as the current qword pointer. the counters are large enough to allow a maximum dma contiguous block transfer of 16 kb (less 1 qword). each channel {x} is handled uniquely and specifically for operating mode, priority, and data rate. recall that the peripheral is in control of initiating, aborting, and ending the dma transfer requests. pointers are 22-bit programmable and dword-aligned. the pointer registers are bit- aligned to represent the pointers as 24-bit byte-addresses. thus the pointer registers should be written and read as 24-bit byte-addresses. however, the lower two bits are fixed at 2?b00 forcing the pointers to be dword-aligned. recall that data transfer resolution is limited to whole qwords.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 4-3 4.4 dmac register memory map dmac registers are identified in table 4-3. table 4-3. dmac registers register label register name asb address type default value ref. dmac_1_ptr1 dmac 1 current pointer 1 0x00300000 rw* 0x00000000 4.5.1 dmac_2_ptr1 dmac 2 current pointer 1 0x00300004 ro 0x00000000 4.5.1 dmac_3_ptr1 dmac 3 current pointer 1 0x00300008 rw* 0x00000000 4.5.1 dmac_4_ptr1 dmac 4 current pointer 1 0x0030000c ro 0x00000000 4.5.1 dmac_5_ptr1 dmac 5 current pointer 1 0x00300010 rw* 0x00000000 4.5.1 dmac_6_ptr1 dmac 6 current pointer 1 0x00300014 rw* 0x00000000 4.5.1 dmac_7_ptr1 dmac 7 current pointer 1 0x00300018 rw* 0x00000000 4.5.1 dmac_8_ptr1 dmac 8 current pointer 1 0x0030001c rw* 0x00000000 4.5.1 dmac_9_ptr1 dmac 9 current pointer 1 0x00300020 rw* 0x00000000 4.5.1 dmac_10_ptr1 dmac 10 current pointer 1 0x00300024 rw* 0x00000000 4.5.1 dmac_11_ptr1 dmac 11 current pointer 1 0x00300028 rw* 0x00000000 4.5.1 *** reserved *** 0x0030002c dmac_1_ptr2 dmac 1 indirect/return pointer 2 0x00300030 rw* 0x00000000 4.5.4 dmac_2_ptr2 dmac 2 indirect/return pointer 2 0x00300034 rw* 0x00000000 4.5.4 dmac_3_ptr2 dmac 3 indirect/return pointer 2 0x00300038 rw* 0x00000000 4.5.4 dmac_4_ptr2 dmac 4 indirect/return pointer 2 0x0030003c rw* 0x00000000 4.5.4 dmac_5_ptr2 dmac 5 indirect/return pointer 2 0x00300040 rw* 0x00000000 4.5.4 *** reserved *** 0x00300044? 0x0030005c dmac_1_cnt1 dmac 1 buffer size counter 1 0x00300060 rw* 0x00000000 4.5.3 dmac_2_cnt1 dmac 2 buffer size counter 1 0x00300064 rw* 0x00000000 4.5.3 dmac_3_cnt1 dmac 3 buffer size counter 1 0x00300068 rw* 0x00000000 4.5.3 dmac_4_cnt1 dmac 4 buffer size counter 1 0x0030006c rw* 0x00000000 4.5.3 dmac_5_cnt1 dmac 5 buffer size counter 1 0x00300070 rw* 0x00000000 4.5.3 dmac_6_cnt1 dmac 6 buffer size counter 1 0x00300074 rw* 0x00000000 4.5.3 *** reserved *** 0x00300078? 0x0030007c dmac_9_cnt1 dmac 9 buffer size counter 1 0x00300080 rw* 0x00000000 4.5.3 dmac_10_cnt1 dmac 10 buffer size counter 1 0x00300084 rw* 0x00000000 4.5.3 dmac_11_cnt1 dmac 11 buffer size counter 1 0x00300088 rw* 0x00000000 4.5.3 *** reserved *** 0x0030008c? 0x00300090 dmac_2_cnt2 dmac 2 buffer size counter 2 0x00300094 wo 0x00000000 4.5.4 *** reserved *** 0x00300098 dmac_4_cnt2 dmac 4 buffer size counter 2 0x0030009c wo 0x00000000 4.5.4 *** reserved *** 0x003000a0? 0x003000fc dmac_12_ptr1 dmac 11 current pointer 1 0x00300100 rw* 0x00000000 4.5.1 dmac_13_ptr1 dmac 12 current pointer 1 0x00300104 rw* 0x00000000 4.5.1 *** reserved *** 0x00300108? 0x0030010c dmac_12_cnt1 dmac 11 buffer size counter 1 0x00300110 rw* 0x00000000 4.5.3 dmac_13_cnt1 dmac 12 buffer size counter 1 0x00300114 rw* 0x00000000 4.5.3 *** reserved *** 0x00300118? 0x00300124
cx82100 home network processor data sheet 4-4 conexant proprietary and confidential information 101306c 4.5 control register formats 4.5.1 dmac x current pointer 1 (dmac_{x}_ptr1) bit(s) type default name description 31:24 reserved. 23:2 rw* 22?bx dmac_{x}_ptr1 current dma qword address pointer. points to next qword transfer location within source or destination buffer. always dword-aligned. 1:0 reserved. 4.5.2 dmac x indirect/return pointer 1 (dmac_{x}_ptr2) bit(s) type default name description 31:24 reserved. 23:2 rw* 22?bx dmac_{x}_ptr2 indirect or return dma qword address pointer. points to next pointer which points to next qword transfer location within source or destination buffer. always dword-aligned. 1:0 reserved. 4.5.3 dmac x buffer size counter 1 (dmac_{x}_cnt1) bit(s) type default name description 31:26 reserved. 25:24 rw 2?b00 dmac_{x}_lmode dma linked list mode. 00 = ptr/cnt at buffer tail. 01 = ptr/cnt at ptr2 (table). 10 = ptr/cnt at ptr2 (return ptr). 11 = reserved. 23:11 reserved. 10:0 rw* 11?bx dmac_{x}_cnt1 initialize to dma buffer size in no. of qwords. decrements during dma data transfers and reloads at end of buffer. note that a write to dmac_{x}_cnt1 also loads buffer size to dmac_{x}_cnt2. 4.5.4 dmac x buffer size counter 2 (dmac_{x}_cnt2) bit(s) type default name description 31:11 reserved. 10:0 rw* 11?bx dmac_{x}_cnt2 saved dma buffer size in no. of qwords.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 4-5 4.5.5 dmac x buffer size counter 3 (dmac_{x}_cnt3) bit(s) type default name description 31:11 reserved. 10:0 rw* 11?bx dmac_{x}_cnt3 saved dma buffer size in no. of qwords.
cx82100 home network processor data sheet 4-6 conexant proprietary and confidential information 101306c 4.6 three basic modes of address generation 4.6.1 source or destination mode dmac_{x}_ptr1 is initialized by the microcontroller to point to the beginning of a dword-aligned source or destination buffer. this pointer advances (by 1 qword) after each transfer request x{x}r. reading this pointer returns the current qword location to be handled next by the dmac when it processes the channel request. 4.6.2 circular buffer modes two circular buffer modes are supported: ? the direct circular buffer for the downstream usb receive data channels. ? the indirect circular pointer table for the ethernet receive channels. direct circular buffer figure 4-1 depicts how the addresses are generated in the direct circular buffer mode. figure 4-1. address generation in direct circular buffer mode 101545_010 dmac_{x}_cnt2 dmac_{x}_cnt1 ? ? ? ? base pointer dmac_{x}_ptr2 ? = dmac_{x}_cnt2 - dmac_{x}_cnt1 top bottom + 8* ? ? ? ? current pointer dmac_{x}_ptr1 dmac_{x}_cnt1 -1 (fixed) (fixed) (moving) (moving) 8 bytes
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 4-7 the usage of each register for controlling the operation of the circular buffer is as follows: ? dmac_{x}_ptr2. used as a base pointer to a dword-aligned circular buffer and is loaded by the microcontroller (by writing to dmac_{x}_ptr1) just once (i.e., this pointer value is fixed) after the buffer has been allocated. this buffer is typically big enough to handle multiple data packets (packet size is 64 bytes for usb). the buffer must be a whole multiple of qwords. ? dmac_{x}_ptr1. used as the current pointer, pointing to the next qword to be transferred. this pointer is constructed by adding 8*(dmac_{x}_cnt2 ? dmac_{x}_cnt1) to the base pointer dma{x}_ptr2. the constructed dmac_{x}_ptr1 is the value read when reading its register location (writing has no effect for the circular buffer mode). ? dmac_{x}_cnt1. loaded with an 11-bit value representing the size of the entire circular buffer. the same value is copied to dmac_{x}_cnt2 during write to dmac_{x}_cnt1. this counter register is decremented by one as a qword transfer is processed. when dma{x}_cnt1 = 0, it is reloaded with dmac_{x}_cnt2. ? dmac_{x}_cnt2. loaded with an 11-bit value representing the size of the entire circular buffer. this value is not changed during the course of data transfers. indirect circular pointer table the indirect circular pointer table is explained with an example of how the emac rxd channels work. the emac-rxd channel (channel 2 or 4) requires its data to be stored in memory buffers where the location of each buffer is chosen by the firmware on a pointer per packet basis. each received data packet is stored in a contiguous memory segment of fixed size. this size must be large enough to handle the largest expected packet (plus overhead), usually less than 1536 bytes (192 qwords). the data is normally going to remain stationary until transmitted or consumed. the circular data buffer method is not appropriate for this channel because it would require the data to be consumed in the order received otherwise the data would have to be copied to other buffers which consumes a lot of bus bandwidth. the dma_{x}_ptr2, where {x} = 2 or 4, is used to point to the location of the table which contains the list of pointers to be used for the received data destination buffers. this table holds the following 4-dword structures called cluster descriptors: table 4-4. cluster descriptor table cluster descriptor table (cdt) ? ? ? ? dma_{x}_ptr2, where {x} = 2 or 4 cd no. qword dword cluster pointer 1 1 reserved emac-rxd status [31:0] for packet 1 1 2 emac-rxd status [63:32] for packet 1 cluster pointer n 2n-1 reserved emac-rxd status [31:0] for packet n n 2n emac-rxd status [63:32] for packet n the cluster descriptors include status that is written back from the emac for each received packet. when dma_{x}_ptr2 is written, a copy is saved as the base pointer to the head of the pointer table (cdt). the dma_{x}_ptr2 can be read anytime to indicate where the dmac is currently at in the cdt. the cdt is a circular buffer. the size in
cx82100 home network processor data sheet 4-8 conexant proprietary and confidential information 101306c qwords is determined by dma_{x}_cnt2. if there are n cluster descriptors then the value 2n should be written to dma_{x}_cnt2. the dmac prefetches the cluster pointers to a two-pointer queue using a source dma channel. this queue is initialized (filled) automatically as soon as the firmware writes to dma_{x}_cnt2 (so cdt must be valid and dma_{x}_ptr2 initialized). the dmac has a two-pointer queue in order to reduce the latency seen by the emac-rxd channel when switching from one cluster to another. the dmac does not want to add the cluster pointer fetch latency to the data transfer latency. the current pointer in the queue is dma_{x}_ptr1 and points to the location in the cluster buffer where the received data is to be stored. this pointer can be read anytime. the dma_{x}_cnt1 value is used to limit the number of qwords the emac-rxd can write to the cluster buffer. writing a value x to this register will cause all qwords dma transferred past x to be stored in the same cluster location (overwritten, only last qword visible). reading this register will return a value that indicates the number of qwords transferred which could be even larger than the size written to dma_{x}_cnt1. this register limits how far the dma_{x}_ptr1 may advance. the dma_{x}_cnt1 value increments by 1 for each dma_xnxt as well as dma_xnul. the emac-rxd dma channel uses a state machine to control the interactions of the firmware, emac-rxd dma requests, and the dmac. this state machine is initialized when dma_{x}_cnt2 is written. this event triggers the prefetch of two cluster pointers from the cdt. the dma_{x}_ptr2 will be pointing to the first emac-rxd status qword location after it fills its dma_{x}_ptr1 queue. when the emac-rxd channel issues dma_xsav, the packet status is read and transferred to the current dma_{x}_ptr2 location. the receiver channel then issues dma_intr which causes the packet interrupt. it also triggers this state machine to transfer the prefetched cluster pointer to dma_{x}_ptr1 and then prefetch the next cluster pointer. at the beginning of each packet the emac-rxd channel issues a dma_save to save a copy of the dma_{x}_ptr1 cluster head pointer. in case of a bad packet (too short, bad crc, etc.) the emac-rxd channel will abort the packet and issue a dma_reld. this event will cause the copy of the cluster head pointer to be reloaded into dma_{x}_ptr1 and the dma_{x}_cnt1 to be re-initialized to zero. the clusters (received packets) consist of received data qwords transferred via dma_xnxt surrounded by reserved qwords at the head and tail of the buffers. table 4-5. received data packet qword no. cluster qword ? ? ? ? dma_{x}_ptr1, {x} = 2 or 4 1 reserved < dma_xnul 2 emac-rxd < dma_xnxt p-1 emac-rxd < dma_xnxt p reserved (0) < dma_xnxt ?? x maximum length of packet data x+1 overflow location for too long packet the 1 st reserved qword is present because the emac-rxd channel issues a dma_xnul at the beginning of every packet. the last reserved qword results from the channel issuing a dma_xnxt to transfer a zero qword. if dma_{x}_cnt1 is set to x, then all qwords received after that limit for a given packet will be transferred to location dma_{x}_ptr1 + 8(x+1). the dma_xnul does increment dma_{x}_cnt1. most packets will end much shorter than the programmed limit. in the case of a too long received packet, the emac will end up aborting the packet which causes the next packet
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 4-9 to be stored at the same cluster location. the limiter, dma_{x}_cnt1, is used to prevent the emac-rxd channel from overwriting the allocated cluster buffer size. the protocol for this dma channel is: 1. arm initializes the cdt. 2. arm initializes dma_{x}_ptr2 with the base pointer to cdt (a copy saved within dmac). 3. arm initializes dma_{x}_cnt1 to limit number of qwords written to cluster. 4. arm initializes dma_{x}_cnt2 for cdt circular size in qwords. 5. dmac prefetches first cluster pointer from dma_{x}_ptr2+ = 8 (post-increments by 8). 6. dmac moves prefetched cluster pointer into dma_{x}_ptr1 and prefetches second cluster pointer from dma_{x}_ptr2+8 (no post-increment). 7. emac-rxd issues dma_save, dmac saves cluster head ptr. 8. emac-rxd issues dma_xnul, dma_{x}_ptr1+ = 8, dma_{x}_cnt1++. 9. emac-rxd issues dma_xnxt, dmac saves data to dma_{x}_ptr1+ = 8, dma_{x}_cnt1++. 10. continue with step 8 until entire packet data is received. 11. emac-rxd issues dma_xsav, dmac saves status to dma_{x}_ptr2+ = 16. 12. emac-rxd issues dma_xnxt, dmac saves 0 to dma_{x}_ptr1+ = 8, dma_{x}_cnt1++. 13. emac-rxd issues dma_intr, dmac sets dma interrupt for rxd channel. 14. dmac moves prefetched cluster pointer into dma_{x}_ptr1 and prefetches next cluster pointer from dma_{x}_ptr2+8 (no post-increment). the arm may read dma_{x}_ptr2 at anytime to know where the dmac is currently processing the table (recall that the dmac is prefetching cluster pointers). the arm can also determine that a emac-rxd status qword location has been updated by looking at bit 3 which is always written with a 1?b1, if it initializes the status qwords with zero and as it consumes clusters (and ptrs). since the cdt operates in circular mode, all ptr2 prefetches and post-increments operate modulo 8*dma_cnt2. 4.6.3 linked list mode there are two linked list modes supported in the current design: 1) embedded tail linked list descriptor mode and 2) indirect/table linked list descriptor mode. the first mode is supported for all transmit channels except channel 7 (memory-to-memory dmas). the second mode is supported only for usb transmit channels, i.e., channels 9, 10, 11, and 13. the linked list mode can be programmed through the "dmac_{x}_lmode" field in the dmac_{x}_cnt1 registers. embedded tail linked list descriptor mode for the embedded tail linked list descriptor mode, the buffer link descriptor (ptr/cnt) is embedded in the buffer at its tail end. figure 4-2 shows an example for this linked list mode. this tail linked list is a generic example of how the transmitted packets are set up. the ctl_hdr is specific to the type of dma being performed, e.g., emac, and should be configured accordingly.
cx82100 home network processor data sheet 4-10 conexant proprietary and confidential information 101306c figure 4-2. embedded tail linked list descriptor example 101545_010 0x00140248 0x0014024c 0x00140250 0x00140254 0x00140258 0x0014025c 0x00140260 0x00140264 0x00140268 0x0014026c 0x00140470 0x00140474 0x00140478 0x0014047c 0x00140480 0x00140484 0x00140488 next cnt1 0x0014048c dmac_{x}_cnt2 = 0x004 dmac_{x}_ptr2= 0x00140248 3 next ptr1 data data data data 0 1 2 ctl hdr data 0x00000003 0x00140470 4 data data data data 2 3 data data 1 data ctl hdr 0 dmac_{x}_cnt1 = 0x001 dmac_{x}_ptr1= 0x00140480 4 bytes
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 4-11 the usage of each register for controlling the operation of the embedded tail linked list descriptor mode is described below. ? dmac_{x}_ptr1: loaded with an initial pointer to a dword-aligned source buffer. a copy of the pointer is automatically saved in dmac_{x}_ptr2 whenever dmac_{x}_ptr1 is loaded with a new pointer. as each dma request is processed, dmac_{x}_ptr1 is incremented by one qword. ? dmac_{x}_cnt1: loaded with the number of qwords to be delivered to the channel. this value includes the ctl_hdr, but not the link fields at the tail. a copy of the counter value is automatically saved in dmac_{x}_cnt2 whenever dmac_{x}_cnt1 is loaded with a new value. as each dma request is processed, dmac_{x}_cnt1 is decremented by one qword. ? dmac_{x}_ptr2: saves the beginning address of the current buffer in the list. this pointer is required for emac re-transmission support. ? dmac_{x}_cnt2: saves the number of qwords to be delivered in the buffer pointed by dmac_{x}_ptr2. this counter is required for emac re-transmission support. when dmac_{x}_cnt1 = = 1, the dmac will actually do two qword asb transfers, forwarding a qword to the apb, and keeping a qword to reload its current pointer (dmac_{x}_ptr1 < = 1 st dword of buffer?s appended qword) and counter (dmac_{x}_cnt1 < = 2 nd appended dword) for processing the next buffer. thus the link to the next source buffer is found at the tail of the current source buffer. when using the embedded tail linked list descriptor for the emac transmission channels (channels 1 and 3), the channels require "re-transmission" support. the re-transmission support is outlined below for channel {x}. 1. when dmac_{x}_ptr1 is loaded, automatically save a copy to dmac_{x}_ptr2. 2. when dmac_{x}_cnt1 is loaded, automatically save a copy to dmac_{x}_cnt2. 3. at anytime the channel may decide to abort the packet and restart by signaling: x{x}r < = dma_reld. this causes the dmac to re-initialize dmac_{x}_ptr1 and dmac_{x}_cnt1 to dmac_{x}_ptr2 and dmac_{x}_cnt2, respectively. it is acceptable for a re- transmission to begin after the channel has linked to other successive buffers. the channel always re-starts at the beginning of the chain. the emac transmission channels also require support for "going back to a saved pointer" and saving a qword containing status of the transmitted packet. a qword can be saved at the saved pointer (usually the start-of-pkt ptr, saved for restart) by signaling: x{x}r < = dma_xsav. this event does not affect the state of the current qword pointer. this data transfer request is asking the dmac to perform a data transfer in an opposite direction for a normal transmitter source channel. however, this is very easy for the dmac to handle. to leave room for status to flow back to the data structure, the transmitter source channel must use dma_save to save a pointer to the status section. it probably does not need to open a hole with dma_xnul since it can overwrite data at the head or tail of the data structure.
cx82100 home network processor data sheet 4-12 conexant proprietary and confidential information 101306c indirect/table linked list descriptor mode the example shown in figure 4-3 illustrates the use of the indirect/table linked descriptor mode for four transmit buffers. the dmac operation is virtually identical to that of the embedded tail linked list descriptor mode except that the next dma ptr1 and cnt1 will be fetched from a pre-programmed pointer/counter table. the table itself is operated in a circular fashion, meaning that the dmac will automatically fetch the next pointer/counter pair from the top of the table as soon as the last pointer/counter pair has been used. the base address of the table is pre-stored in the dmac_{x}_ptr2 register. the size of the table (in number of qwords) is pre-stored in the dmac_{x}_cnt2 register. note that dmac_{x}_ptr1 and dmac_{x}_cnt1 registers should be initialized to contain the ptr1/cnt1 values associated with the first buffer. the same ptr1/cnt1 values should also be stored at the bottom of the table in order to make the four buffers work together like a big circular buffer. figure 4-3. indirect/table linked list descriptor example 1 101545_012 dmac_{x}_cnt1 = 0x01000009 4 bytes 0x001400f8 0x001400fc 0x00140100 64-byte data packet #1 0 0x0014013c 8 0x00140140 descriptor/status 0x001402f8 0x001402fc 0x00140300 64-byte data packet #2 0 0x0014033c 8 0x00140340 descriptor/status 0x001404f8 0x001404fc 0x00140500 64-byte data packet #3 0 0x0014053c 8 0x00140540 descriptor/status 0x001406f8 0x001406fc 0x00140700 64-byte data packet #4 0 0x0014073c 8 0x00140740 descriptor/status dmac_{x}_ptr1= 0x001400f8 address 0x001402f8 0x01000009 0x001404f8 0x01000009 0x001406f8 0x01000009 0x001400f8 0x01000009 0x00140800 0x00140804 0x00140808 0x0014080c 0x00140810 0x00140814 0x00140818 0x0014081c address dmac_{x}_cnt2 = 0x00000004 dmac_{x}_ptr2= 0x00140800
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 4-13 the use of the tail and the indirect/table linked list descriptor modes can be mixed to form a more complicated list. the dynamic switch from one mode to the other is controlled by the pre-programmed value in dmac_{x}_lmode. figure 4-4 shows an example for mixing the two modes with five buffers. figure 4-4. indirect/table linked list descriptor example 2 101545_013 dmac_{x}_cnt1 = 0x01000009 4 bytes 0x001400f8 0x001400fc 0x00140100 64-byte data packet #1 0 0x0014013c 8 0x00140140 descriptor/status 0x001402f8 0x001402fc 0x00140300 64-byte data packet #2 0 0x0014033c 8 0x00140340 descriptor/status 0x001404f8 0x001404fc 0x00140500 64-byte data packet #3 0 0x0014053c 8 descriptor/status dmac_{x}_ptr1= 0x001400f8 address 0x001402f8 0x01000009 0x001404f8 0x00000009 0x001408f8 0x01000009 0x001400f8 0x01000009 0x00140800 0x00140804 0x00140808 0x0014080c 0x00140810 0x00140814 0x00140818 0x0014081c address dmac_{x}_cnt2 = 0x00000004 dmac_{x}_ptr2= 0x00140800 0x00140540 0x001406f8 0x01000009 0x00140544 0x001406f8 0x001406fc 0x00140700 64-byte data packet #4 0 0x0014073c 8 0x00140840 descriptor/status 0x001408f8 0x001408fc 0x00140900 64-byte data packet #4 0 0x0014093c 8 0x00140940 descriptor/ status
cx82100 home network processor data sheet 4-14 conexant proprietary and confidential information 101306c this page is intentionally blank.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 5-1 5 host interface description the host interface operates in master mode which allows the hnp to access external flash rom and an optional slave device. the host interface master mode operates asynchronously and is not referenced to any host clock input or output. 5.1 master mode 5.1.1 host master mode interface signals the host master mode consists of a 21-bit output address bus, 16-bit bidirectional data bus, read enable output, write enable output, flash rom chip enable output, spare chip enable output, and spare interrupt request input. in master mode, the host interface is selected to drive the host control/address/data interface when the host asb slave dsel is active. host master mode signals are illustrated in figure 5-1 and listed in table 5-1. figure 5-1. host master mode signals 101306_016 had[15:0] 16 had[29:16], hc[7:1] 21 hcs0# hnp hwr# hrd# hcs4# hirq4# host interface had[29:16], hc[7:1] had[15:0] hc09 hc08 hc00 had31 gpio25 spare (uart example) flash rom a[20:0] d[15:0] wr# rd# ce# a[3:1] d[7:0] wrua# rdua# ce# irq# had[15:0] 16 had[29:16], hc[7:1] 21 hcs0# hw r# hrd# had[7:0] 8 hc[3:1] 3 hw r# hrd# hcs4# hirq4#
cx82100 home network processor data sheet 5-2 conexant proprietary and confidential information 101306c table 5-1. host master mode signals pin signal host master mode signal pin no. signal direction signal name had[15:0] hd[15:0] n7, m9, l8, k9, j9, n10, p10, m10, l9, k10, l10, m11, j10, l11, n12, p12 i/o host bus data [15:0] had[29:16] ha[20:7] l3, l1, m2, m1, n2, n1, m3, n3, p3, m4, n4, p4, l4, m5 o host bus address [20:7] hc[07:01] ha[6:0] l5, m6, k6, n6, p6, l6, p7 o host bus address [6:0] hc08 (hrd#) hrd# m13 o host bus read enable hc09 (hwr#) hwr# m12 o host bus write enable hc10 (hrdy#) hrdy# p14 (cx82100-41/-42) i handshake for slow peripherals hc00 (hcs0#)/gpio32* hcs0# p14 (cx82100-11/-51/-52) p13 (cx82100-41/-42) o host chip select 0 (flash rom) had31 (hcs4#)/gpio31* hcs4# j8 o host chip select 4 (spare) notes: * = these pins default to host functions; they can be reconfigured to gpio pins. the hnp host master mode supports only the little-endian mode data byte orientation. as depicted in figure 5-2, the 32-bit little-endian asb data bus bd[31:0] is mapped to/from the 16-bit external host data bus hd[15:0] according to the even/odd half-word (16 bits) data address alignment indicated by the address bit ha1. figure 5-2. little-endian mode data bus mapping 101545_15 7:0 15:8 hd 31:24 7:0 15:8 23:16 bd[31:0] to/from asb bd even half-word address: ha1 = 0 7:0 15:8 hd odd half-word address: ha1 = 1 31:24 7:0 15:8 23:16 bd[31:0] to/from asb bd the asb side may address the host as a slave in 16-bit or 32-bit mode. the 32-bit mode accesses are converted to two external 16-bit accesses. the host interface is allocated 5 mb total address space. this address space is allocated to the six chip selects hcs[5:0]# as shown in figure 5-1 and table 5-2.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 5-3 table 5-2. chip select address ranges hcs signal typical slave device asb address range size hcs0# (hc00) flash rom 0x00400000?0x007fffff 4 mb hcs4# (had31) application dependent 0x002c0000?0x002cffff 64 kb 5.1.2 flash memory interface the master mode host interface addresses up to 32 mbit (2 m x 16) of flash rom using ha[21:1]. hcs0# is designed specifically to select flash rom. flash rom can be optionally used for the hnp executable memory instead of internal rom. typically, a 32 mbit (2 m x 16) flash rom such as an intel te28f320c3ba90 or equivalent, or a 16 mbit (1 m x 16) flash rom such as an intel te28f160c3ba90 or equivalent, is used. the hnp supports only 16-bit flash memories, therefore, all writes to a 16-bit flash must be word transfers. refer to section 3.4 for a description of booting from flash rom. 5.1.3 interfacing to other slave devices the peripheral interface is completely programmable via the host control registers. these registers allow programming of parameters such as peripheral bus width (8-bit or 16-bit), timing for both read and write operations, and control signal polarity. during a transfer with an 8-bit peripheral, bit 0 of the address, which is omitted when interfacing to a 16-bit peripheral, is issued on hd15. (this pin is available in 8-bit mode because the data bus is using only bits hd[7:0].) during a transfer with a 16-bit peripheral, there are two byte-write enables (one for the lower 8 bits of the transfer and another for the upper 8 bits), which allow for individual byte writes to 16-bit peripherals which support such transfers. the high-byte write enable is assigned to pin had29 and the low-byte write enable is assigned to pin hc09. when writing data to a 16-bit device which does not support multiple byte write enables, the host must ensure that writes to the device are initiated internally as either word or dword transfers. 5.1.4 host master mode dma engine both asynchronous and isochronous modes of operation are available and are selected by the msb (bit 9) of the hdma_mode_sel field in the hst_ctrl register. asynchronous dma transfer mode in asynchronous dma transfer mode, data transfers complete as fast as the source and destination bus environments allow. isochronous dma transfer mode in isochronous dma transfer mode, the data is transferred to or from the external peripheral at a specified rate. the user supplies the isochronous transfer rate using an internal timer, as selected by the hdma_mode_sel field in the hst_ctrl register. this rate can be programmed by the hdma_isoc_timer field in the hdma_timers register.
cx82100 home network processor data sheet 5-4 conexant proprietary and confidential information 101306c if internal dma timer is selected, a value must be written to hdma_isoc_timer. this value is, in terms of bclk periods, the time between dma accesses to the external peripheral. for example, when dmaing data from a peripheral to an internal destination this register value determines the rate data is read from the peripheral. the transfer rate is also a function of the peripheral?s data bus width. for example, if hdma_isoc_timer is set to 200 and the peripheral is set up as an 8-bit wide device, then 200 bclk periods will elapse between each byte transaction with the peripheral. if the same value is programmed, in the case of a 16-bit peripheral, the same 200 bclk periods will elapse between each word transaction with the peripheral. thus, the data rate in the case of the 16-bit peripheral is twice that of the 8-bit peripheral, even though the hdma_isoc_timer is set to the same value in both cases. general dma information a host-dma transfer is configured from the asb side via the hdma_source_addr, hdma_dest_addr, and hdma_bcnt registers. the host-dma transfer is started as soon as the hdma_bcnt register is written to with a nonzero value. for this reason, the hdma_bcnt register should only be written to once the hdma_source_addr and hdma_dest_addr registers contain the appropriate values. dma_src_addr_inc_disable is a 1-bit field in the hst_ctrl register. when enabled, the dma transfer always occurs from the 24-bit address programmed into the hdma_source_addr. this is needed when a dma transfer originates from a register that takes its data sequentially from a fifo. dma_dst_addr_inc_disable is a 1-bit field in the hst_ctrl register. its purpose is similar to that of dma_src_addr_inc_disable except that it transfers data to a static address location set in hdma_dest_addr. hdma_mode_sel is a 2-bit field in the hst_ctrl register with the msb being the enable for isochronous mode, and the lsb determining the variation of isochronous mode. the hdma_source_addr register is a 24-bit register that should be written with the address of the first byte of data to be transferred via the host-dma. the hdma_dest_addr register is a 24-bit register that should be written with the byte address of the destination for the host-dma data. the hdma_bcnt register is a 22-bit register that should be written to with the number of bytes to be transferred after writing to the hdma_source_addr and hdma_dest_addr. once the number of bytes has been written into the register, the host dma transfer begins. the hdma_isoc_timer is an 8-bit field in the hdma_timers register that is used when hdma_mode_sel is set to 2?b10. this register is programmed with a value, in terms of bclk periods, equal to the length of time between consecutive external dma accesses. the completion of a host-dma transfer is signaled by the setting of the int_host interrupt (bit 6 of int_stat register). this bit can be cleared by writing a 1 to the bit. subsequent host-dma transfers must not be initiated until the previous host-dma transfer has been completed.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 5-5 5.1.5 host master mode timing (cx82100-11/-12/-51/-52) host master mode read operation (accessing an external device) the host master mode read timing is illustrated in figure 5-3 and listed in table 5-3. ? hrd# and hwr# signals are used when the appropriate bit of the host master mode transfer control register is low. ? hr/w# and hds# signals are used when the appropriate bit of host master mode transfer control register is high. ? tpw is programmable via the host master mode read wait-state control registers (hst_rwst). host master mode write operation (accessing an external device) the host master mode write timing is illustrated in figure 5-4 and listed in table 5-4. ? hrd# and hwr# signals are used when the appropriate bit of the host master mode transfer control register is low. ? hr/w# and hds# signals are used when the appropriate bit of host master mode transfer control register is high. ? tpw is programmable via the host master mode write wait-state control registers (hst_wwst).
cx82100 home network processor data sheet 5-6 conexant proprietary and confidential information 101306c figure 5-3. waveforms for host master mode read operation (cx82100-11/-12/-51/-52) 100603_017 tpw tds tdh tas tcsh hds# tcss hd[15:0] hcs[x]# hrd# hwr# ha[21:1] hr/w# address data tah table 5-3. timing for host master mode read operation based on a 100 mhz bclk (cx82100-11/-12/-51/-52) symbol parameter min. max. units tas programmable address setup to active read 10 160 ns tpw programmable read pulse width 10 320 ns tds required data setup to end of active read 5 ? ns tdh required data hold time following active read 40 240 ns tah programmable address hold time following active read 40 90 ns tcsh programmable chip select hold time relative to re# or r/w# 0 150 ns tcss programmable chip select setup time relative to re# or r/w# 0 150 ns
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 5-7 figure 5-4. waveforms for host master mode write operation (cx82100-11/-12/-51/-52) 101603_018 tpw tas tcsh hds# tcss hd[15:0] hcs[x]# hrd# hwr# ha[21:1] hr/w# address tadh data table 5-4. timing for host master mode write operation based on a 100 mhz bclk (cx82100-11/-12/-51/-52) symbol parameter min. max. units tas programmable address setup to active write 10 160 ns tpw programmable read pulse width 10 320 ns tadh programmable address and data hold time following active write (address hold time is longer that data hold time so min. and max. is based on the address hold time). 50 200 ns tcsh programmable chip select hold time relative to we# or r/w# 0 150 ns tcss programmable chip select setup time relative to we# or r/w# 0 150 ns
cx82100 home network processor data sheet 5-8 conexant proprietary and confidential information 101306c 5.1.6 host master mode timing (cx82100-41/-42) host master mode read operation (accessing an external device) the host master mode read timing is illustrated in figure 5-5 and listed in table 5-5. ? hrd# and hwr# signals are used when the appropriate bit of the host master mode transfer control register is low. ? hr/w# and hds# signals are used when the appropriate bit of host master mode transfer control register is high. ? tpw is programmable via the host master mode read wait-state control registers (hst_rwst). ? hrdy# is used for handshaking when the appropriate bit of the host master mode peripheral handshake register is set. host master mode write operation (accessing an external device) the host master mode write timing is illustrated in figure 5-6 and listed in table 5-6. ? hrd# and hwr# signals are used when the appropriate bit of the host master mode transfer control register is low. ? hr/w# and hds# signals are used when the appropriate bit of host master mode transfer control register is high. ? tpw is programmable via the host master mode write wait-state control registers (hst_wwst). ? hrdy# is used for handshaking when the appropriate bit of the host master mode peripheral handshake register is set.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 5-9 hrdy# description (cx82100-41/-42) hrdy# is used to extend a host interface operation. the use of hrdy# can be enabled or disabled by setting or clearing the corresponding hrdy# handshake enable bit in the mstr_handshake register (0x002d0024). when hrdy# is enabled, the polarity of hrdy# can be programmed by setting or clearing bit 0 of the mstr_handshake register. ? with hrdy# polarity low (default polarity, bit 0 of 0x002d0024 = 0), hrdy# low indicates the target on the host bus is ready/waiting and hrdy# high indicates the target is busy. in this case, chip selects hcs0#-hcs5# will assert when hrdy# is low and will not assert when hrdy# is high. ? with hrdy# polarity high (bit 0 of 0x002d0024 = 1), hrdy# high indicates the target on the host bus is ready/waiting and hrdy# low indicates the target is busy. in this case, chip selects hcs0#-hcs5# will assert when hrdy# is high and will not assert when hrdy# is low. when hrdy# is enabled, the pulse widths of hrd# and hwr# are controlled by either the hrdy# signal or the timing specified by the host read/write wait state control register, whichever has longer cycle time. hrd# and hwr# will never have a smaller width than the programmed values thus minimum host interface cycle time is guaranteed. when hrdy# is disabled, the state of hrdy# is ignored and the timing of the host interface control and data signals are controlled by the timing configuration registers: hst_rwst, hst_wwst, hst_read_cntl1, hst_read_cntl2, hst_write_cntl1, and hst_write_cntrl2.
cx82100 home network processor data sheet 5-10 conexant proprietary and confidential information 101306c figure 5-5. waveforms for host master mode read operation (cx82100-41/-42) 100545_079 tpw tds tdh tas tcsh hds# hrdy# tcss hd[15:0] hcs[x]# hrd# hwr# ha[21:1] hr/w# address data tah table 5-5. timing for host master mode read operation based on a 100 mhz bclk (cx82100-41/-42) symbol parameter min. max. units tas programmable address setup to active read 10 160 ns tpw programmable read pulse width 10 320 ns tds required data setup to end of active read 5 ? ns tdh required data hold time following active read 40 240 ns tah programmable address hold time following active read 40 90 ns tcsh programmable chip select hold time relative to re# or r/w# 0 150 ns tcss programmable chip select setup time relative to re# or r/w# 0 150 ns
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 5-11 figure 5-6. waveforms for host master mode write operation (cx82100-41/-42) 101545_080 tpw tas tcsh hds# hrdy# tcss hd[15:0] hcs[x]# hrd# hwr# ha[21:1] hr/w# address tadh data table 5-6. timing for host master mode write operation based on a 100 mhz bclk (cx82100-41/-42) symbol parameter min. max. units tas programmable address setup to active write 10 160 ns tpw programmable read pulse width 10 320 ns tadh programmable address and data hold time following active write (address hold time is longer that data hold time so min. and max. is based on the address hold time). 50 200 ns tcsh programmable chip select hold time relative to we# or r/w# 0 150 ns tcss programmable chip select setup time relative to we# or r/w# 0 150 ns
cx82100 home network processor data sheet 5-12 conexant proprietary and confidential information 101306c 5.2 host master mode register memory map host master mode registers are identified in table 5-7. table 5-7. host master mode registers register label register name asb address type default value ref. hst_ctrl host control register 0x002d0000 rw 0x00000008 5.3.1 hst_rwst host master mode read-wait-state control register 0x002d0004 rw 0x00739ce7 5.3.2 hst_wwst host master mode write-wait-state control register 0x002d0008 rw 0x00739ce7 5.3.3 hst_xfer_cntl host master mode transfer control register 0x002d000c rw 0x00000000 5.3.4 hst_read_cntl1 host master mode read control register 1 0x002d0010 rw 0x00000000 5.3.5 hst_read_cntl2 host master mode read control register 2 0x002d0014 rw 0x00000000 5.3.6 hst_write_cntl1 host master mode write control register 1 0x002d0018 rw 0x00000000 5.3.7 hst_write_cntl2 host master mode write control register 2 0x002d001c rw 0x00000000 5.3.8 mstr_intf_width host master mode peripheral size 0x002d0020 rw 0x00000000 5.3.9 mstr_handshake host master mode peripheral handshake 0x002d0024 rw 0x00000000 5.3.10 hdma_src_addr host master mode dma source address 0x002d0028 rw 0x00000000 5.3.11 hdma_dst_addr host master mode dma destination address 0x002d002c rw 0x00000000 5.3.12 hdma_bcnt host master mode dma byte count 0x002d0030 rw 0x00000000 5.3.13 hdma_timers host master mode dma timers 0x002d0034 rw 0x00000000 5.3.14
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 5-13 5.3 host master mode registers 5.3.1 host control register (hst_ctrl: 0x002d0000) bit(s) type default name description 31:12 reserved. 11 r/w 1'b0 dma_src_addr_inc_disable disable dma source address increment. 0 = enable dma source address increment. 1 = disable dma source address increment. 10 r/w 1'b0 dma_dst_addr_inc_disable disable dma destination address increment. 0 = enable dma destination address increment. 1 = disable dma destination address increment. 9:8 rw 2?b00 hdma_mode_sel host master mode dma transfer mode select. 00 = asynchronous dma mode. 01 = reserved. 10 = isochronous dma mode using internal timer. 11 = reserved. 7 reserved. 6 rw 1?b0 en_block_arm enable the arbiter to lock 940 adr/seq/ and bursts. 0 = disable arbiter to lock 940 adr/seq/ and bursts. 1 = enable arbiter to lock 940 adr/seq/ and bursts. 5 reserved. 4 rw 1?b0 run_map run-time memory map. 0 = flash rom @ starting address 0x00000000, internal ram @ starting address 0x00180000. 1 = internal ram @ starting address 0x00000000, flash rom @ starting address 0x00180000. 3:2 rw 2?b10 xdm_sz external dynamic memory size. 00 = 2 mb. 01 = 4 mb. 10 = 8 mb. 11 = reserved. 1:0 rw 2?b00 hst_hirq hirq0# output state for external host. 0x = off. 10 = asserted low. 11 = de-asserted and pulled high.
cx82100 home network processor data sheet 5-14 conexant proprietary and confidential information 101306c 5.3.2 host master mode read-wait-state control register (hst_rwst: 0x002d0004) bit(s) type default name description 31:25 reserved. 24:20 rw 5?b00111 hst_rws4 hcs4 wait state control for master mode read cycles. length of read cycle = count value * 1 bclk period + 1 bclk period. 19:5 reserved. 4:0 rw 5?b00111 hst_rws0 hcs0 wait state control for master mode read cycles. length of read cycle = count value * 1 bclk period + 1 bclk period. 5.3.3 host master mode write-wait-state control register) (hst_wwst: 0x002d0008) bit(s) type default name description 31:25 reserved. 24:20 rw 5?b00111 hst_wws4 hcs4 wait state control for master mode write cycles. length of read cycle = count value * 1 bclk period + 1 bclk period. 19:5 reserved. 4:0 rw 5?b00111 hst_wws0 hcs0 wait state control for master mode write cycles. length of read cycle = count value * 1 bclk period + 1 bclk period. 5.3.4 host master mode transfer control register (hst_xfer_cntl: 0x002d000c) bit(s) type default name description 31:8 reserved. 7 rw 1?b0 hcs4_ds_polarity hcs4 external data strobe polarity. 0 = negative data strobe polarity. 1 = positive data strobe polarity. 6:4 reserved. 3 rw 1?b0 hcs4_xfer_mode hcs4 external transfer mode. 0 = we# and re# transfer mode. 1 = r/w# and ds# transfer mode. 2:0 reserved. 5.3.5 host master mode read control register 1 (hst_read_cntl1: 0x002d0010) bit(s) type default name description 31:28 rw 4?b0 hrcs4_tcss hcs4 chip select setup time relative to re# or r/w#. length = count value * 1 bclk period. 27:16 reserved. 15:12 rw 4?b0 hrcs4_tcsh hcs4 chip select hold time relative to re# or r/w#. length = count value * 1 bclk period. 11:0 reserved.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 5-15 5.3.6 host master mode read control register 2 (hst_read_cntl2: 0x002d0014) bit(s) type default name description 31:28 rw 4?b0 hrcs4_tas hcs4 address setup time to active read. length = count value * 1 bclk period + 1 bclk period. 27:16 reserved. 15:12 rw 4?b0 hrcs4_tah hcs4 and hcs5 address hold time following active read. length count value * 1 bclk period + 4 bclk periods. 11:0 reserved. 5.3.7 host master mode write control register 1 (hst_write_cntl1: 0x002d0018) bit(s) type default name description 31:28 rw 4?b0 hwcs4_tcss hcs4 chip select setup time relative to we# or r/w#. length = count value * 1 bclk period. 27:16 reserved. 15:12 rw 4?b0 hwcs4_tcsh hcs4 chip select hold time relative to we# or r/w#. length = count value * 1 bclk period. 11:0 reserved. 5.3.8 host master mode write control register 2 (hst_write_cntl2: 0x002d001c) bit(s) type default name description 31:28 rw 4?b0 hrcs4_tas hcs4 address setup time to active write. length = count value * 1 bclk period + 1 bclk period. 27:16 reserved. 15:12 rw 4?b0 hrcs4_tadh hcs4 address and data hold time following active write. for data, length = count value * 1 bclk period + 1 bclk period. for address, length count value * 1 bclk period + 5 bclk periods. 11:0 reserved. 5.3.9 host master mode peripheral size (mstr_intf_width: 0x002d0020) bit(s) type default name description 31:5 reserved. 4 rw 1?b0 mstr_intf_width4 hcs4 data length. 0 = 16-bit data length. 1 = 8-bit data length. 3:0 reserved.
cx82100 home network processor data sheet 5-16 conexant proprietary and confidential information 101306c 5.3.10 host master mode peripheral handshake (mstr_handshake: 0x002d0024) (cx82100-41/-42) bit(s) type default name description 31:5 reserved. 4 rw 1?b0 mstr_handshake4 hcs4 hrdy# handshake enable. 0 = disable hrdy# handshake. 1 = enable hrdy# handshake. 3:1 reserved. 0 rw 1?b0 mstr_handshake0 hrdy# polarity. 0 = active low 1 = active high 5.3.11 host master mode dma source address (hdma_src_addr: 0x002d0028) bit(s) type default name description 31:24 reserved. 23:0 rw 24?b0 hdma_source_addr least significant 24 bits of the address of the first byte of dma source data. 5.3.12 host master mode dma destination address (hdma_dst_addr: 0x002d002c) bit(s) type default name description 31:24 reserved. 23:0 rw 24?b0 hdma_dest_addr least significant 24 bits of the first location of the dma destination. 5.3.13 host master mode dma byte count (hdma_bcnt: 0x002d0030) bit(s) type default name description 31:22 reserved. 21:0 rw 22?b0 hdma_byte_count the number of bytes of data to be transferred via the host dma. 5.3.14 host master mode dma timers (hdma_timers: 0x002d0034) bit(s) type default name description 31:16 reserved. 15:8 rw 8?b0 hdma_isoc_timer timer which dictates the transfer rate for an isochronous mode dma transfer in terms of the number of bclk periods. 7:0 rw 8?b0 hdma_inactive_timer the minimum interval, in terms of number of bclk periods, between subsequent accesses to an external dma source or destination.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 6-1 6 external memory controller interface description 6.1 pc100 compliant sdram interface the external memory controller (emc) provides a 16-bit interface to support up to 8 mb of external sdram. figure 6-1 shows a typical sdram functional block diagram. note that the actual sdram design varies from vendor to vendor. figure 6-1 also shows an intel pc100 compliant interface between the emc and the sdram. table 6-1 lists the definition for each interface signal. a pc100 compliant sdram must also support a mode register whose functions are defined in table 6-2. the mode register is programmable through the mrs (mode register set) command defined in the pc100 specification (see reference [6]). figure 6-1. sdram interface 101545_025 data i/o + control logic ra decode + control logic control logic command refresh bank banks (2x or 4x) mode register ca decode + control logic external memory controller mm[1:0] md[15:0] asb mb[1:0] ma[11:0] mras# mcas# mwe# mcs# mcke mclk sdram hnp
cx82100 home network processor data sheet 6-2 conexant proprietary and confidential information 101306c table 6-1. emc sdram interface signal descriptions pin name i/o signal name description md[15:0] i/o memory data bi-directional data access bus for dram. ma[11:0] o memory address multiplexed row and column address for access of data up to 8 mb. mb[1:0] o bank address selects active memory bank. mm[1:0] o memory mask input mask signal for write accesses. mras# o row address strobe starts sdram access with strobe of row address. mcas# o column address strobe strobes column address and data bytes. mwe# o memory write enable indicates write access to sdram. mcs# o memory chip select enables the sdram command decoder. mcke o memory clock enable memory clock activation. mclk o memory clock all sdram signals sampled on positive edge. table 6-2. pc100 compliant mode register bit no. name supported function 11:7 reserved. 6:4 ltmode cas# latency. 011 = 3 cycles. all other = reserved. 3wt wrap type. 0 = linear. 1 = interleave. 2:0 bl burst length. 011 = 8 cycles. all other = reserved. the sdram clock runs at 100 mhz, however, 125 mhz rated sdram is required in order to guarantee setup time margin.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 6-3 6.2 available vendor sdram ics and features although the emac is not fully pc100 compliant due to the fact that both the cas# latency and the burst length are hard wired, many other pc100 compliant vendor sdrams are usable for the emac design. table 6-3 lists some of these sdrams and their corresponding features and access timings. table 6-3. available sdram vendors 1m x 16 x 4 sdram input output initialization sequence spec./ vendor basic features ref. rate clock cycle setup hold valid hold valid to z intel pc100 spec. (rev. 1.63) cl = 2,3 bl = 1,2,4 burst read burst write auto refresh period: 10 ns high: 3 ns low: 3 ns 2 ns 1 ns cl = 3: 6 ns c l = 2: 6 ns 3 ns min: 3 ns max: 9 ns 200 s -> precharge -> 8rf -> mrs-> 1st command micron mt48lc4m16a2 cl = 1,2,3 bl = 1,2,4,8,fp burst read burst write single write auto refresh self refresh 15.6 s cl = 3: 8 ns cl = 2: 10 ns 2 ns 1 ns cl = 3: 6 ns cl = 2: 6 ns 1.8 ns cl = 3: 6 ns cl = 2: 7 ns 100 s -> precharge -> 2rf min -> mrs -> 1st command samsung km416s4030d cl = 2,3 bl = 1,2,4,8,fp burst read burst write auto refresh self refresh 15.6 s period: 10 ns 2 ns 1 ns cl = 3: 6 ns cl = 2: 6 ns 3 ns cl = 3: 6 ns cl = 2: 7 ns 100 s -> precharge -> 2rf min -> mrs-> 1st command fujitsu mb81f641642d cl = 2,3 bl = 2,4,8,fp burst read burst write single write auto refresh self refresh 15.6 s period: 10 ns high: 3 ns low: 3 ns 2 ns 1 ns cl = 3: 6 ns cl = 2: 6 ns 3 ns min: 3 ns max: 6 ns 100 s -> precharge -> 2rf min -> mrs-> 1st command nec pd4564841-10 cl = 2,3 bl = 1,2,4,8,fp burst read single write auto refresh self refresh 15.6 s cl = 3: 10 ns cl = 2: 13 ns high: 3 ns low: 3 ns 2 ns 1 ns cl = 3: 6 ns cl = 2: 7 ns 3 ns cl = 3: 6 ns cl = 2: 7 ns min: 3 ns 200 s -> precharge -> 2rf min -> mrs-> 1st command ibm 19l3264-10 cl = 2,3 bl = 1,2,4,8,fp burst read single write auto refresh self refresh 15.6 s cl = 3: 10 ns cl = 2: 15 ns 3 ns 1 ns cl = 3: 7 ns cl = 2: 8 ns 3 ns min: 3 ns max: 7 ns 200 s -> precharge -> 8rf -> mrs-> 1st command toshiba tc59s6416bft- 10 cl = 2,3 bl = 1,2,4,8,fp burst read single write auto refresh self refresh 15.6 s 10 ns 2.5 ns 1 ns 7 ns 3 ns min: 3 ns max: 10 ns 200 s -> precharge -> 8rf -> mrs-> 1st command
cx82100 home network processor data sheet 6-4 conexant proprietary and confidential information 101306c 6.3 supported configurations table 6-4 lists supported sdram configurations. there are only one or two memory ics at most that reside on the external sdram bus (e.g., two 2m x 8 sdrams are required to get 4 mb). this bus is not shared with any other external function. since the emc buffers write data phases, this pipelined activity implies that the sdram bus can be busy concurrently with asynchronous and independent host bus transfers. (an external host can read/write sdram as well.) table 6-4. allowed sdram configurations total memory memory config. no. of sdrams sdram config. sdram capacity sdram no. of banks sdram no. of rows sdram no. of columns 2 mb 1mb x 16 1 1mb x 16 16 mb 2 2kb 256 4 mb 2mb x 16 2 2mb x 8 16 mb 2 2kb 512 8 mb 4mb x 16 1 4mb x 16 64 mb 4 4kb 256 6.4 access cycles the emc?s sdram 16-bit interface is synchronous. all of the sdram inputs are registered on the positive edge of mclk. the sdram uses an internal pipelined architecture to achieve high-speed operation. read and write accesses to the sdram are burst oriented (it's been noted from the simulation that the emac design only allows read accesses to the sdram to be burst oriented). a burst of 8 allows a cache line (16 bytes) to be refilled in one single read. accesses begin with the registration of an active command, which is then followed by a read or write command. 6.5 initialization the sdram requires a 200 s delay prior to applying an executable command. the delay begins after reset when power and clock are stable. the microcontroller should not access the sdram during this time, otherwise all processes will be held up while the emc inserts wait states for the full initialization duration. no user intervention is required during the initialization process. all appropriate settings are managed by the sdram controller. 6.6 refresh the sdram controller supports auto-refresh. refresh requests are generated to meet a 15.625 s per row interval (to be safe, it is preferable that refresh requests could be generated at a rate less than 15.625 s per row interval). refresh cycles are transparent to the host, but will insert wait cycles if the memory is accessed during a refresh request. refresh requests have top priority when accessing the memory. refresh cycles will not interrupt a memory cycle in process.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 6-5 6.7 read no acceleration is provided for read accesses. multiple memory banks allow multiple rows to be active simultaneously. this reduces the need for precharge and activate cycles, allowing a faster aggregate throughput. 6.8 write a 2-dword buffer is provided to speed up random and dma write accesses. 6.9 throughput better than 114 mb/s for 16-byte cache-line fills and 177 mb/s for buffered 16-byte writes. random read or write single accesses operate at 50 mb/s and 200 mb/s, respectively. table 6-5 summarizes the throughput for each access type. table 6-5. sdram throughput 16-bit sdram interface no. of bclk cycles 32-bit access 1 dword 4 dwords (seq burst) write 2 9 read 8 14 write immediately following write 2 15 read immediately following read 12 18 16-bit access 1 word 4 words (seq burst) write 2 8 read 7 10 write immediately following write 2 11 read immediately following read 12 12
cx82100 home network processor data sheet 6-6 conexant proprietary and confidential information 101306c 6.10 emc i/o clock interface and timing the emc i/o clock interface is illustrated in figure 6-2. the emc i/o timing is illustrated in figure 6-3. figure 6-2. emc clocking interface 101545_026 clkgen module pad bclk mclk ext_sdram asb_sdram d q pad md hnp pad ma d q bclk scan mux scan mux scan mux mclk ma md figure 6-3. emc i/o timing 101545_027 bclk mclk data md addr ma a = tck-q + tdsm + tpo b = tasu c = clock skew = tdi + tdsm + tpo d = ta e = tsu + tpi + tdsm f = (clk period / 2) - tdi - tdsm - tpo notes: where: a b c d e f tck-q = asb_sdram flop clk-q delay tsu = asb_sdram flop setup time th = asb_sdram flop hold time tdsm = hnp scan mux delay tpo = output pad delay tpi = input pad delay tdi = hnp inverter delay ta = sdram read access time
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 6-7 6.11 sram interface the hnp emc can alternatively interface to sram memory. the sdram associated pins are used for this interface and are multiplexed to either interface to sdram or sram. sdram or sram interface is controlled by the emcr register and allows for different external sizes and up to two sram devices. using two 512-kbyte sram devices (256k x 16 each), a maximum of 1 mb of external sram can be achieved. the emcr register controls for sram read/write wait state control, selection of one or two memory chips, and selection of various sizes for each of the memories. the sdram-to-sram signal mapping is shown in table 6-6. if one srams are used, connect ce_sram1# to the sram ce# (chip enable) and leave ce_sram2# open. if two srams are used, connect ce_sram1# to the lower address range sram (sram 1) ce# and ce_sram2# to the upper address range sram (sram 2) ce#. for the srams, connect oe# (output enable), ble# (byte low enable), and bhe# (byte high enable) to vss. table 6-6. hnp to sdram/sram interface signal mapping hnp pin signal sdram interface sram pin signal mcke cke a17 mcas# mcas# a16 mb1 mb1 a15 mb0 mb0 a14 mm1 mm1 a13 mm0 mm0 a12 ma[11:0] a[11:0] a[11:0] md[15:0] d[15:0] io[15:0] mcs# cs# ce# (sram 1) mras# ras# ce# (sram 2) mwe# we# we#
cx82100 home network processor data sheet 6-8 conexant proprietary and confidential information 101306c 6.12 emc register the emc register is identified in table 6-7. table 6-7. emc register register label register name asb address type default value ref. emcr external memory control register 0x00350010 rw 0x00000000 6.12.1 6.12.1 external memory control register (emcr: 0x00350010) bit(s) type default name description 7:6 rw 2?b00 srwsc sram read/write wait state control. 00 = no extra delay. 01 = delayed by one bclk period. 10 = delayed by two bclk periods. 11 = delayed by three bclk periods. note: the delay cycles are extra to the normal access cycles. 5:4 rw 2?b00 srcsel2 sram chip select 2. 00 = do not select the second sram chip. 01 = select the second sram chip, size = 64k x 16. 10 = select the second sram chip, size = 128k x 16. 11 = select the second sram chip, size = 256k x 16. notes: 1. exmsel must be 2?b10 if the second sram chip is selected. 2. the size for the second sram must be no greater than the size of the first sram. 3. if the second sram size is programmed at a value greater than that of the first sram, then the actual size for the second sram will be reduced to the same size as the first automatically by the hardware. 3:2 rw 2?b00 srcsel1 sram chip select 1. 00 = do not select the first sram chip. 01 = select the first sram chip, size = 64k x 16. 10 = select the first sram chip, size = 128k x 16. 11 = select the first sram chip, size = 256k x 16. note: exmsel must be 2?b10 if the first sram chip is selected. 1:0 rw 2?b00 exmsel external memory select. 00 = select sdram interface; sdram in disabled mode. 01 = select sdram interface; sdram in enabled mode. 10 = select sram interface. 11 = reserved.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 7-1 7 ethernet media access control interface description the hnp implements the ethernet media access control (emac) as defined in reference [4]. also implemented is the mii interface to the physical layer as defined in reference [5]. in the osi reference model as shown in figure 7-1, the lowest layer is physical and the next layer up is data link. the data link layer is segmented into 2 parts, medium access control (mac) which interfaces to the phy, and the logical link control (llc) which interfaces to the mac and to higher layers. figure 7-1. mac sublayer partition, relationship to osi reference model 101545_028 reconciliation pma pls reconciliation pma pls pmd physical network transport session presentation application data link pma osi reference model layers lan csma/cd layers higher layers aui 1 mb/s, 10 mb/s 10 mb/s 100 mb/s aui = attachment unit interface mdi = medium dependent interface mii = media independent interface pls = physical layer signaling pma = physical medium attachment pmd = physical medium dependent pls medium medium medium mii mii mdi mdi llc - logical link control mac - media access control the llc together with the mac must provide the following data link functionality: ? data encapsulation (transmit and receive) ? framing (frame boundary delimitation, frame synchronization) ? addressing (handling of source and destination addresses) ? error detection (detection of physical medium transmission errors) ? media access management ? medium allocation (collision avoidance) ? contention resolution (collision handling)
cx82100 home network processor data sheet 7-2 conexant proprietary and confidential information 101306c 7.1 mac frame format figure 7-2 shows the mac frame format supported by the hnp (see section 3.1.1 of reference [4]). as depicted in the figure, the bytes of a frame are transmitted from top to bottom. the bits of each byte in each field (with the exception of the fcs) are transmitted from the lsb to msb (i.e., lsb transmitted first). figure 7-2. ethernet mac frame format 101545_029 preamble llc data length source address (sa) destination address (da) start frame delimiter (sfd) frame check sequence (fcs) pad 2 or 6 bytes 7 bytes 2 or 6 bytes 1 byte 2 bytes (variable) (variable) 4 bytes bytes w ithin frame transmitted from top-to-bottom defined in standard preamble llc data length source address (sa) destination address (da) start frame delimiter (sfd) frame check sequence (fcs) pad 6 bytes 7 bytes 6 bytes 1 byte 2 bytes (variable) (variable) 4 bytes implemented fields involved in fcs computation at the head of the mac frame is the 7-byte preamble 0xaa aa aa aa aa aa aa followed by the 1-byte start of frame delimiter (sfd) 0xab. the mac receiver must detect the sfd pattern 0xab. after sfd the mac must begin receiving the frame (assuming the carrier sense signal is asserted). the address fields are the next fields in the frame. first is the 48-bit destination address followed by the 48-bit source address. then comes the 2-byte length field. then comes the llc data and any pad bits required so the frame size is the minimum allowable (which is 64 bytes not including fcs). finally, we have the 4 byte frame check sequence (fcs) which is a crc to check for frame errors due to ethernet phy (ephy) transmission impairments. all fields except the preamble, sfd, and fcs are used to compute the crc. the crc generating polynomial is g(x) = x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x+1. the 32 bits of the crc value are placed in the fcs field so that the x 31 term is the leftmost bit of the first byte of the field, and the x 0 term is the rightmost bit of the last byte of the field. the bits of the fcs field are thus transmitted in the order x 31 , x 30 , ..., x 2 , x 1 , x 0 .
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 7-3 7.2 parameterized values used in implementation table 7-1 shows the values of the standard parameters used in the emac implementation. these parameters are defined in sections 4.4.2.1 of reference [4] and 4.4.2.3 of reference [5]. the value specified for the interframe gap (ifg) parameter determines the speed of the ethernet. it is defined to be 96 s for 1 mb/s implementation, 9.6 s for 10 mb/s implementation, and 0.96 s for 100 mb/s implementation. only the 10 mb/s and 100 mb/s implementations are supported in the hnp. the ifg parameter is programmable through the ethernet network access register (bits 17:16 of e_na_1 and e_na_2 for emac1 and emac2, respectively). table 7-1. parameterized values implemented in emac parameter values slottime 512 bit times ifg (interframe gap) programmable attemptlimit 16 backofflimit 10 jamsize 32 bits maxframesize 1518 bytes minframesize 512 bits (64 bytes) addresssize 48 bits
cx82100 home network processor data sheet 7-4 conexant proprietary and confidential information 101306c 7.3 emac functional features the emac block supports the mac sublayer of the ieee 802.3 and allows it to be connected to an ieee 802.3 10/100 mbps (100base-t and 10base-t) mii compatible ephy device. the emac block supports the following features: ? for frame transmission ? accepts data from host and constructs a frame ? presents nibble data stream to the ephy ? for frame reception ? receives nibble data stream from the ephy ? presents to the host frames that are either broadcast/multicast frames or directly addressed to the local station ? discards or passes to the host all frames not addressed to it (programmable) ? defers transmission whenever the medium is busy ? delays transmission of frame for specified interframe gap (ifg) period ? appends preamble, sfd, fcs to frames, and inserts pad field for frames whose data length is less than minframesize ? halts transmission when collision is detected ? enforces collision to ensure propagation throughout network by sending jam message ? schedules retransmission after a collision until attemptlimit is reached ? checks received frames for transmission errors by way of fcs ? discards received frames that are less than minframesize. ? removes preamble and sfd. fcs and pad field (if necessary) from received frames are passed along. ? ieee 802.3u mii physical layer interface ? full-duplex or half-duplex operation ? normal and internal loopback mode ? linked list transmit data structures for scatter/gather support. ? programmable data padding and fcs capability ? address filtering (promiscuous, perfect, inverse and hash filtering) ? programmable ifg ? generates signals for software to maintain mib (management information base) status in software ? management data interface (mdi) to an mii compliant ephy ? qword (64-bit) interface to the dma controller in half-duplex mode, the hnp checks the line condition before starting to transmit. if the condition is clear, it starts transmitting (after ifg). transmit enable (emx_txen) asserts and data is transferred through the mii port.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 7-5 full-duplex operation allows simultaneous transmission and reception of data, which can effectively double data throughput to 20 or 200 mb/s. in full-duplex mode, the hnp starts transmitting a frame provided that ifg duration time has elapsed since its previous transmission. since there is no collision in full-duplex mode, the transmission always ends successfully. the hnp monitors the line for a new frame transmission in both half and full duplex modes. a new frame transmission is defined as both transmit data valid and carrier sense asserted. the following features of the emac should be taken into account: ? the fcs is defined as a 32-bit field, which means the minimum number of data bytes required for a meaningful fcs is 4 (i.e. you can not generate a 32-bit fcs from data that is shorter than 32-bits). packets which are less than 4 bytes long, should not be checked for fcs. ? received emac frames are padded to align to qword boundaries, during reception, prior to dmac transfer. however, the length that is used in the length status field is calculated prior to the padding insertion. this length field, fl, bits 31-16 of the rmac in-line status qword, is provided in bytes. this length, fl, includes the entire frame that was transmitted, including crc, but it does not include the padding bytes that were added by the emac receiver to align to the qword boundary. the next frame is defined to start at the beginning of that same qword boundary. ? setting up the emac receiver for address filtering is done by directly programming all filter related register bits (e_na_hp, e_na_ho, e_na_if, e_na_pr, and e_na_pm) via writes to the e_na register. ? if an rx fifo overflow interrupt occurs, the rx should be reset via bit e_na_rrx in the e_na register. the most recently written packet in the rx circular buffer is damaged, and must be aborted by the software.
cx82100 home network processor data sheet 7-6 conexant proprietary and confidential information 101306c 7.4 emac architecture block diagram of the emac unit is shown in figure 7-3. figure 7-3. emac functional block diagram 101545_030 dma interface apb tx buffer manager (tbm) txfifo sync mac transmitter tmac rx buffer manager (rbm) rxfifo sync mac receiver rmac etxd[3:0] erxd[3:0] etxck erxck hnp the emac module interfaces with the dma controller through the dma interface block. the apb address is decoded in this block. tx buffer manager (tbm) and rx buffer manager (rbm) blocks control the mac transmitter and mac receiver, respectively. tbm and rbm issue the requests to the dma controller and control their own fifos. synchronization is required between the mac receiver and the rbm because they operate on different clocks (pclk and emx_rx_clk, respectively). similarly, synchronization is required between the mac transmitter and the tbm because they operate on different clocks (pclk and emx_tx_clk, respectively).
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 7-7 7.5 media independent interface (mii) the mii provides a port for transmit and receive data that is media independent, multi- vendor interoperable, and supports all data rates and physical standards. the port consists of data paths that are 4 bits wide in each direction as well as control and management signals. figure 7-4 shows the mii connector with signal names and the contact assignment. figure 7-4. mii connector 1015435_031 1 20 21 40 +5v erxd[3:0] mdc mdio erxdv erxck erxer etxer etxck etxen etxd[3:0] ecol ecrs +5v +5v +5v grounds (22-39) 50 mm 15 mm the primary function of the mii is to provide the interface to the ephy and necessary digital interface for ephy management. the mii management interface utilizes a communications protocol similar to a serial eeprom. the 10/100 mac mii interface provides all services required by the mii, including encoding and decoding of mii.
cx82100 home network processor data sheet 7-8 conexant proprietary and confidential information 101306c 7.6 emac interrupts the emac provides three interrupts each for emac1 and emac2: ? int_emac#{x}_err (diagnostics/exception interrupt) ? int_dmac_emac#{x}_rx (packet received interrupt) ? int_dmac_emac#{x}_tx (transmission complete interrupt) where {x} indicates the emac number (1 or 2). these interrupt bits are located in the int_stat register (see section 11.2.2). int_emac#{x}_err is set to 1 if any number of emac interrupts occur. before an emac interrupt can be recognized by the hnp, its corresponding enable bit must be set to 1 in e_ie_{x}. the equation for the int_emac#{x}_err is as follows: int_emac#{x}_err = (e_ie_au and e_lp_au) or (e_ie_ai and (e_s_es or e_s_tuf or e_s_tof or e_s_ro or e_s_tjt or e_s_rwt)) or e_ie_ni and (e_lp_ri or e_lp_ti) or (e_ie_tu and e_s_tu) or (e_ie_rw and e_s_rwt) or (e_ie_tof and e_s_tof) or (e_ie_tuf and e_s_tuf) or (e_ie_ed and e_s_ed) or (e_ie_df and e_s_df) or (e_ie_rld and e_s_rld) or (e_ie_tf and e_s_tf) or (e_ie_tjt and e_s_tjt) or (e_ie_ncrs and e_s_ncrs) or (e_ie_lcrs and e_s_lcrs) or (e_ie_16 and e_s_16) or (e_ie_lc and e_s_lc) or (e_ie_ri and e_lp_ri) or (e_ie_ti and e_lp_ti) int_dmac_emac#{x}_rx bit field is set to 1 in the int_stat register after the receiver posts the status in the status field of the rx buffer for a good packet when e_na_pb bit of e_na_{x} is 0 (do not pass bad packet). when e_na_pb is set to 1 (pass bad or good packet), the int_dmac_emac#{x}_rx bit is set after the receiver post the status for a good or bad packet. int_dmac_emac#{x}_tx bit field is set to 1 in the int_stat register after the transmitter posts the status of the packet in the tx buffer or when the transmitter gets a stop descriptor (ready bit in the tdes is zero).
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 7-9 7.7 tmac architecture before the host requests transmission of a frame, it constructs the data (llc data) field of the frame in memory. the tmac appends a preamble and a sfd to the beginning of the frame. using information from the descriptor, tmac also appends a pad at the end of the data field of sufficient length to ensure that the transmitted frame length satisfies a minimum frame. tmac then attempts to avoid contention with other traffic on the medium by monitoring the carrier sense signal provided by the ethernet phy and deferring to passing traffic. when the medium is clear, frame transmission is initiated (after a brief interframe delay to provide recovery time for other devices on the medium). the tmac then provides data nibbles to the ephy on the mii. the ephy monitors the medium and generates the collision detect signal, which, in the contention-free case, remains off for the duration of the frame. when transmission has completed without contention, the tmac informs the host by writing status into the memory and awaits the next request. 7.7.1 transmit frame structure before the tmac can start transmitting a frame containing the llc data, a transmit message structure as shown in figure 7-5 must be constructed by the host in arm's memory. tmac reads data from the memory (via dma channel 1 or 3) to transmit via mii and writes data into the memory to update the status. the arm host is the master for tmac transmit operations and serves data to the tmac via the apb. it is also the host's task to assemble ethernet frames to be sent out by the tmac. the transmit descriptor (tdes), the transmit status (tstat), and the sequence of transmitter dma operation are described below. note that the qword count which is to be loaded into the dmac_{x}_cnt1 register should always include the first qword reserved for the transmit status.
cx82100 home network processor data sheet 7-10 conexant proprietary and confidential information 101306c figure 7-5. emac transmit frame structure 101545-032 next dma cnt (frame #n) next dma ptr (frame #n) data (frame #n) descriptor (tdes frame #n) 0x00000000 status (tstat frame #n) 4 bytes data (frame #n) next dma cnt (frame #n) next dma ptr (frame #n) data n (end of frame #n) data (frame #n) data (frame #n) data (frame #n) next dma cnt (frame #n+1) next dma ptr (frame #n+1) data (frame #n+1) descriptor (tdes frame #n+1) 0x00000000 status (tstat frame #n+1) data (frame #n+1) written by used by requested by tmac & sent to tmac fifo by dmac tmac arm arm arm tmac arm tmac arm dmac requested by tmac & sent to tmac fifo by dmac dmac requested by tmac & sent to tmac fifo by dmac requested by tmac & sent to tmac fifo by dmac tmac arm dmac
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 7-11 7.7.2 transmit descriptor the contents of the transmit descriptor (tdes) are described in table 7-2. table 7-2. transmit descriptor format bit(s) field transmit descriptor (tdes) description 31:17 unused. 16 rdy frame ready. 0 = frame not ready to be transmitted. 1 = frame ready to be transmitted. 15:4 tlen transmit frame length. transmit frame length in bytes. range is 0?4095. this includes the preamble, sfd, da, sa, length, and data to transmit. 3 reserved. 2 set setup frame. 0 = current frame is not a setup frame. 1 = current frame is a setup frame. 1dpd disable tx padding. 0 = enable tx padding. 1 = disable tx padding. 0ac disable crc appending. 0 = enable crc appending. 1 = disable crc appending.
cx82100 home network processor data sheet 7-12 conexant proprietary and confidential information 101306c 7.7.3 transmit status (tstat) the contents of the transmit status (tstat) are described in table 7-3. table 7-3. transmit status format bit(s) default type name description 31 1?b0 tdn transmit completed. 0 = transmit not completed successfully. 1 = transmit completed successfully (from buffer manager). 30 1?b0 tu transmit stopped. 0 = transmit not stopped. 1 = transmit stopped (descriptor not ready). 29:21 unused. 20:17 4?b0 ts transmit state. 0 = mii transmitter state inactive. 1 = mii transmitter state active (except during setup frames). for test only. 16 1?b0 ** tof transmit buffer manager fifo overflow. 0 = transmit buffer manager fifo overflow has not occurred (mib11). 1 = transmit buffer manager fifo overflow has occurred. 15 1?b0 ** tuf transmit buffer manager fifo underflow. 0 = transmit buffer manager fifo underflow has not occurred (mib11). 1 = transmit buffer manager fifo underflow has occurred (mib11). 14 1?b0 ** ed excessive transmit deferrals. 0 = excessive deferral did not occur. 1 = the hnp is attempting to transmit and is deferred longer than: 10 mbps: 8192 x 400 ns 100 mbps: 81920 x 40 ns 13 1?b0 ** df frame deferred. 0 = frame has not been deferred at least once (mib8). 1 = frame has been deferred at least once (mib8). 12 1?b0 *, ** cd frame transmit completed. 0 = frame transmit not completed successfully (from mii interface). 1 = frame transmit completed successfully (from mii interface). 11 1?b0 ** es transmit error summary. 0 = frame has not been deferred at least once (mib8). 1 = transmitter error summary (tf or c16 or lc or ncrs or lcrs or tjt). 10 1?b0 ** rld reload. 0 = frame has not been deferred at least once (mib8). 1 = transmit fifo reload/abort during frame (includes collisions). 91?b0*, **tf transmit fault (from mii interface). 0 = unexpected transmit data request during frame has not occurred. 1 = unexpected transmit data request during frame has occurred. 81?b0 tjt transmit jabber timeout. 0 = jabber timer not expired. 1 = jabber timer expired. e_na_huj and e_na_huj must be configured for this bit to function.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 7-13 bit(s) default type name description 7 1?b0 ** ncrs no carrier. 0 = no carrier (emx_crs pin never gone high) during frame transmit. 1 = no carrier (emx_crs pin never transitioned high) during frame transmit. 6 1?b0 ** lcrs lost carrier. 0 = carrier was not lost during frame transmit. 1 = carrier was lost (emx_crs pin transitioned low) at least once frame transmit (mib18). 51?b0*, **c16 16 or more collisions. 0 = 16 or more collisions have not occurred during frame transmit. 1 = 16 or more collisions have occurred during frame transmit. 41?b0*, **lc late collision. 0 = a late collision (after the 64th byte) has not occurred during frame transmit. 1 = a late collision (after the 64th byte) has occurred during frame transmit (mib16). 3:0 4?b0 ** cc collision count. transmit collision count of the frame. resets after the frame is transmitted successfully (mib9). increments with every collision of the current frame. * this field resets to its default value at the start of every transmit attempt (successful or unsuccessful termination) ** this field resets to its default value after a successful transmit.
cx82100 home network processor data sheet 7-14 conexant proprietary and confidential information 101306c 7.7.4 sequence of transmitter dma operation tmac dma operation is illustrated in figure 7-6. figure 7-6. tmac dma operation for channel {x} = 1 or 3 101545_033 host programes the base pointer dmac_{x}_ptr1 and the length dmac_{x}_cnt1 for the 1st fragment of the frame host assembles the frame to be transmitted in linked list structure and writes the tdes host sets the e_na_strt bit in register e_na_{x} to cause the tmac to start the transmission tmac starts the dma on channel {x} by issuing the dma_save command to dmac. dmac saves ptr1 to prt2 and cnt1 to cnt2. tmac issues dma_xnxt command to dmac to skip the tstat field. tmac issues dma_xnxt command to dmac to receive the tdes and the 1st 4 bytes of the data. tdes.rdy bit on? tmac issues dma_xnxt commands to f ill up the fifo and starts transmitting nibbles. last double word received? yes no no tmac updates the e_s_tu bit in register e_stat_1 (or e_stat_2) to interrupt the host, providing the bit e_ie_tu is set in register e_ie_1 (or e_ie_2) host reads the bit tstat.tdn to determine the transmission status. tmac transmission stopped. yes tmac issues dma_xsave to request dmac to write the tstat to host memory tmac issues dma_intr to dmac to signal the end of a frame. tmac continues to transmit nibbles in the fifo until completion.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 7-15 7.8 rmac architecture 7.8.1 support for the detection of invalid mac frames as defined in the 802.3 specification, an invalid mac frame meets at least one of the following conditions: ? the frame length is inconsistent with the length field. ? the frame length is not an integral number of bytes. ? the frame bits (excluding fcs) do not generate correct crc value (crc mismatch). the 802.3 specification requires that contents of invalid frames must not be passed to llc. this functional requirement will be handled by software. the software will be supplied status to distinguish valid from invalid frames. this is described as follows: condition 1 the rmac hardware will not parse the type/length field. in the case of a valid frame, the hardware will infer the length based on mii signaling, and pass the length (the fl field) as part of the "status qword" (see section 7.8.5). for invalid frames, the length information may or may not be available to the software. in the case where the type/length field is type, neither hardware nor software will detect this invalid condition. if the type/length field is length, the software will detect this condition. the type/length field indicates whether the frame is in ieee 802.3 format or ethernet format. a field greater than 1500 is interpreted as a type field, which defines the type of protocol of the frame. a field smaller than or equal to 1500 is interpreted as a length field, which indicates the number of data bytes in the frame. condition 2 the rmac hardware will detect this invalid condition and report it in the status qword as bit db (dribble bit). condition 3 the rmac hardware will detect and record this invalid condition by using a local management information base (mib) counter, named "crc" (bits 52-59 of the status qword, see table 7-8). this is an 8-bit counter which will be reset when the rmac hardware detects that a good packet has been read by the dmac. it will be incremented by one when a crc mismatch occurs. this counter is passed to the software as part of the status qword. 7.8.2 support for the reception without contention the 802.3 specification requires that each receiving station is responsible for collecting data bits from mii as long as the carrier sense signal is asserted. when carrier sense is deasserted, the frame is truncated to a byte boundary, if necessary, and passed to receive data decapsulation for processing. receive data decapsulation is required to check the frame?s destination address field to decide if the frame should be received by this station. if so, it passes the destination address, the source address, and llc data unit to
cx82100 home network processor data sheet 7-16 conexant proprietary and confidential information 101306c the llc sublayer along with a status code indicating reception_complete or reception_too_long (longer than 1518 bytes). to support this requirement, address filtering (see section 7.8.4) is to be used. address filtering is very computation intensive since it is required to be performed on every packet on the ethernet, regardless of its intended destination. address filtering will be supported in the rmac hardware for "destination address" only. nevertheless, the software will be capable to program the hardware to promiscuous mode (see page 7-22), which would pass all packets. also, the software will be able to program the hardware to pass bad packets. therefore, the software will have flexibility to handle address filtering if it so chooses. the rmac hardware will also provide hooks to the software to support reception_complete or reception_too_long to allow compliance with the 802.3 specification requirement. these conditions are reported in the status qword. 7.8.3 support for the reception with contention emx_col asserted indicates collision detected. rmac is required to distinguish frame fragments received during collisions from valid frames. it will be implemented in hardware. early collisions will be ignored. late collisions, after dmac transfer initiation, will be reported in the rmac status qword as bit lc (late collision). 7.8.4 address filtering the hnp emac supports address filtering in hardware for full 48-bit ethernet destination addresses only. the process for setting up the address filters and configuring the filtering modes are described in the next few sections. setup frame the tmac and rmac operate independently during normal operation except during setup frames. setup frames are not transmitted on the mii interface but are looped back from the tmac to the rmac and are used to program the address filters. a setup frame defines the ethernet addresses that are used to filter all incoming frames and must be processed before the reception process is started, except when it operates in promiscuous filtering mode . when processing the setup frame, the receiver logic temporarily disengages from the mii interface and the transmission process must be running. the setup frame is processed after all preceding frames have been transmitted and the current frame reception (if any) is completed. the setup frame size must be exactly 192 bytes (see table 7-4). perfect address filtering the hnp system can store up to 16 full 48-bit ethernet destination addresses. rmac compares the destination address of any incoming frame to these addresses and decides whether to reject or accept the frame based on the filtering mode configured in the e_na_1 or e_na_2 register (defined in section 7.11.3). this filtering method is called perfect address filtering (as opposed to the hashing-based imperfect address filtering defined in this section) because it accepts addresses that ? do not match if in inverse filtering mode (defined in this section). ? match if not in inverse filtering mode. table 7-4 shows the perfect address filtering setup frame format in the host memory. the rmac only keeps the column labeled "15....0" in a 48 x 16-bit hardware buffer.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 7-17 table 7-4. setup frame buffer format entry no. bytes bits 31:16 bits 15:0 physical address no. 0 3:0 xxxxxxxxxxxxxxxx bytes [1:0] 1 7:4 xxxxxxxxxxxxxxxx bytes [3:2] 2 11:8 xxxxxxxxxxxxxxxx bytes [5:4] address 0 3 15:12 xxxxxxxxxxxxxxxx bytes [1:0] 4 19:16 xxxxxxxxxxxxxxxx bytes [3:2] 5 23:20 xxxxxxxxxxxxxxxx bytes [5:4] address 1 6 27:24 xxxxxxxxxxxxxxxx bytes [1:0] 7 31:28 xxxxxxxxxxxxxxxx bytes [3:2] 8 35:32 xxxxxxxxxxxxxxxx bytes [5:4] address 2 . . . . . . . . . . . . . . . 45 183:180 xxxxxxxxxxxxxxxx bytes [1:0] 46 187:184 xxxxxxxxxxxxxxxx bytes [3:2] 47 191:188 xxxxxxxxxxxxxxxx bytes [5:4] address 15 note that any mix of physical (i.e., unicast: the first bit of the address is 0) and logical (i.e., multicast or group: the first bit of the address is 1) addresses can be used. unused addresses should be duplicated with one of the valid addresses. example of a perfect address filtering setup frame figure 7-7 displays a perfect address filtering setup frame for two address filters. figure 7-7. a perfect address filtering setup frame buffer 101545_034 ethernet addresses to be filtered: (1) 25-00-26-11-27-22 (2) 09-ab-08-d1-01-15 setup frame in host buffer (little-endian) byte no. setup frame in emac buffer (little-endian) . . . . x x x x x x x x x x x x 32 byte no. x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x repeat last valid address a b d 1 1 5 0 9 0 8 0 1 a b d 1 1 5 0 9 0 8 0 1 a b d 1 1 5 0 9 0 8 0 1 . . . . 0 0 1 1 2 2 2 5 2 6 2 7 0 1 a b d 1 1 5 0 9 0 8 0 1 a b d 1 1 5 0 9 0 8 0 1 a b d 1 1 5 0 9 0 8 0 1 . . . . 0 0 1 1 2 2 2 5 2 6 2 7 0 1 0 47 5 4 3 2 1 6 7 8 46 45 0 47 5 4 3 2 1 6 7 8 46 45 (1) (2)
cx82100 home network processor data sheet 7-18 conexant proprietary and confidential information 101306c imperfect address filtering the hnp system can store 512 bits serving as hash bucket heads to support "multicasting". the purpose of multicasting is to allow a group of nodes in a network to receive the same message. each node can maintain a list of multicast addresses that it will respond to. the multicast address filtering in the hnp system is a hardware-assisted hashing mechanism. it can reduce the amount of cpu time required to determine whether or not the incoming frame, with a multicast destination address, will be accepted. for a given list of multicast addresses that the hnp system will respond to, the hnp software first maps each multicast address into one of the 512 hash bits using the same cyclic redundancy check (crc) algorithm specified in the 802.3 standard. the crc is the 32-bit remainder of dividing a message polynomial (specified in the 802.3 standard) by the generating polynomial g(x) = x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x+1. figure 7-8 shows a division circuit for g(x) using a 32-bit linear feedback shift register. the message bits are shifted in from the left one bit at a time according to the ascending order of x in the polynomial representation of message bits. after all bits are shifted in, the remainder is generated and stored in the register. figure 7-8. a circuit for dividing by g(x) 101545_035 x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 x 9 x 10 x 11 x 12 x 15 ... x 16 x 21 ... x 22 x 23 x 25 .. x 26 x 31 ... x 32 x 26 x 23 x 22 x 16 x 12 x 11 x 10 x 8 x 7 x 5 x 4 x 2 x 1 x 0 g(x) = x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x+1 the same crc algorithm will be used to map each multicast address into one of the 512 hash bits organized as a 32x16 hash table. the table is seen by the software as the lower 16 bits of the first 32 entries of the setup frame. each 6-byte multicast address that the node will respond to is fed into the crc algorithm to generate a 32-bit crc value. the most significant 9 bits of the result is used as an index into a 32x16-bit hash table. the upper 5 bits are used to identify the row of the table and the lower 4 bits are used to point to the bit position of the selected row. the selected bit position will be turned on (set to binary 1) by the software.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 7-19 table 7-5 shows the format for the setup frame involving multicast address filters. note that one physical address filter is included in this setup frame. this is usually the address of the node itself. table 7-5. imperfect address filtering setup frame format entry no. bytes bits 31:16 bits 15:0 0 3:0 xxxxxxxxxxxxxxxx hash table row 0 1 7:4 xxxxxxxxxxxxxxxx hash table row 1 2 11:8 xxxxxxxxxxxxxxxx hash table row 2 . . . . . . . . . . . . . . . . . . . . 29 119:116 xxxxxxxxxxxxxxxx hash table row 29 30 123:120 xxxxxxxxxxxxxxxx hash table row 30 31 127:124 xxxxxxxxxxxxxxxx hash table row 31 32 131:128 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 33 135:132 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 34 139:136 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx . . . . . . . . . . . . . . . 39 159:156 xxxxxxxxxxxxxxxx physical address (bytes [1:0]) 40 163:160 xxxxxxxxxxxxxxxx physical address (bytes [3:2]) 41 167:164 xxxxxxxxxxxxxxxx physical address (bytes [5:4]) 42 171:168 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx . . . . . . . . . . . . . . . 47 191:188 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx when a 48-bit multicast address is received, the rmac hardware uses the same crc algorithm to generate the corresponding crc value. this is shown in figure 7-9. the most significant 9 bits (in little-endian mode, these are the rightmost 9 bits of the 32-bit linear shift register) of the crc value will be used to access a hardware hash table that has been loaded by the setup frame described above. if the hash bit is 1 (a hit), the frame will be accepted and delivered to the host cpu. otherwise, the frame will be rejected. a hit on the hash table does not necessarily mean that the multicast frame delivered to the host is actually destined to this node. it only assures that there is a possibility that the incoming multicast address belongs to the node. to determine if it belongs to the node, the host software must examine the address against the list of multicast addresses to be accepted by this node. this filtering method is called "imperfect" because multicast frames not addressed to this node may slip through (an invalid address may be hashed into a bit location which is turned on by a valid address), but it still decreases the number of frames that the host can receive.
cx82100 home network processor data sheet 7-20 conexant proprietary and confidential information 101306c figure 7-9. imperfect address filtering 101545_036 destination address ig 0 47 46 crc logic hash table (32x16) 32-bit crc 0 8 9 31 0 16 one physical address 0 31 54 hit/miss if ig=0 if ig=1 example of an imperfect address filtering setup frame table 7-6 displays seven multicast addresses to be filtered imperfectly and one unicast address to be filtered perfectly. the corresponding setup frame is displayed in figure 7-10. table 7-6. hash index generated using ethernet crc algorithm multicast/unicast ethernet address 32-bit crc value in little-endian mode hash index: (most significant 9 bits of the crc value) 0xd57701f6 0x1f6 (2) d9-c2-c0-99-0b-82 0x8c14febe 0x0be (3) e7-c1-96-36-89-dd 0x3be71e3c 0x03c (4) 85-00-25-00-27-00 0x4d69365e 0x05e (5) 9d-48-4d-fd-cc-0a 0xd4be5976 0x176 (6) c1-cc-28-55-d3-c7 0x18883cd2 0x0d2 addresses subject to imperfect filtering (7) ab-46-0a-55-2d-7e 0x78081873 0x073 physical address subject to perfect filtering 3a-12-c2-56-de-91 ? ?
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 7-21 figure 7-10. example of imperfect filtering setup frame 101545_037 ethernet addresses to be filtered setup frame in host buffer (little-endian) (1) 0 x x x x 0 0 0 0 1 x x x x 0 0 0 0 2 x x x x 0 0 0 0 3 x x x x 1 0 0 0 4 x x x x 0 0 0 0 5 x x x x 4 0 0 0 6 x x x x 0 0 0 0 7 x x x x 0 0 0 8 8 x x x x 0 0 0 0 9 x x x x 0 0 0 0 a x x x x 0 0 0 0 b x x x x 4 0 0 0 c x x x x 0 0 0 0 d x x x x 0 0 0 4 e x x x x 0 0 0 0 f x x x x 0 0 0 0 x x x x 0 0 0 0 x x x x 0 0 0 0 x x x x 0 0 0 0 x x x x 0 0 0 0 x x x x 0 0 0 0 x x x x 0 0 0 0 x x x x 0 0 0 0 x x x x 0 0 4 0 x x x x 0 0 0 0 x x x x 0 0 0 0 x x x x 0 0 0 0 x x x x 0 0 0 0 x x x x 0 0 0 0 x x x x 0 0 0 0 x x x x 0 0 0 0 x x x x 0 0 4 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 1 2 3 a x x x x 5 6 c 2 x x x x 9 1 d e x x x x x x x x x x x x x x x x x x x x x x x x 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f (2) (3) (4) (5) (6) (6) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 32 0 1 imperfect filtering (1) a3-c5-62-3f-25-87 (2) d9-c2-c0-99-0b-82 (3) e7-c1-96-36-89-dd (4) 85-00-25-00-27-00 (5) 9d-48-4d-fd-cc-0a (6) c1-cc-28-55-d3-c7 (7) ab-46-0a-55-2d-7e perfect filtering 3a-12-c2-56-de-91 setup frame in emac buffer (little-endian) 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 1 2 3 a 5 6 c 2 9 1 d e x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 0 1 hash table physical address byte no. byte no.
cx82100 home network processor data sheet 7-22 conexant proprietary and confidential information 101306c address filtering modes eight different address filtering modes are supported in the hnp. these modes are configured through the e_na_pm, e_na_pr, e_na_if, e_na_ho, and e_na_hp bits of the network access register (see section 7.11.3). table 7-7 lists the combination of these bits to select the desired address filtering mode. each mode is described below. table 7-7. address filtering mode address filtering mode e_na_pm: (pass all multicast) e_na_pr: (receive any good frame) e_na_if: (inverse filtering) e_na_ho: (hash only) e_na_hp: (hash/ perfect filtering) 16 perfect filtering 0 0 0 0 0 inverse filtering 0 0 1 0 0 1 perfect filtering + 512-hash bit imperfect filtering 00001 512-hash bit imperfect filtering only 00011 x100x promiscuous 01011 pass all multicast 1 0 0 1 1 pass all multicast + 16 perfect filtering 10000 pass all multicast + 1 perfect filtering 10001 16 perfect filtering mode. rmac provides support for the perfect filtering of up to 16 ethernet unicast or multicast addresses. any mix of addresses can be used. the 16 addresses used will occupy all of the allocated space in the setup-frame. inverse filtering mode. in this mode, all frames with addresses that match any of the 16 perfect addresses in the setup frame will be rejected. frames with addresses that do not match any of the 16 perfect addresses in the setup frame will be accepted. one perfect filtering + 512-hash bit imperfect filtering mode. rmac supports one, single unicast address to be perfectly filtered with an unlimited number of multicast addresses to be imperfectly filtered. the single address that is to be perfectly filtered will need to reside in byte locations <156, 157>, <160, 161>, <164, 165> of the setup frame. the lower 16 bits of the first 32 entries of the setup frame is treated as a 512-bit hash table for imperfect filtering. this mode supports the needs of applications that require one, single physical address to be filtered as the node's address, while allowing reception of more than 16 multicast addresses without suffering the overhead of passing all multicast frames to the host. 512-hash bit imperfect filtering only mode. rmac supports imperfect filtering for an unlimited number of unicast addresses as well as multicast addresses. the lower 16 bits of the first 32 entries of the setup frame represents a 512-bit hash table. all addresses are used to generate indices into the hash table. frames with addresses causing a hash table hit are passed. this mode supports the needs of applications that require more than one physical address to be filtered as the node's address, while allowing reception of more than 16 multicast addresses without suffering the overhead of passing all multicast frames to the host.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 7-23 promiscuous filtering mode. rmac supports the reception of all good frames on the network, regardless of their destination. this mode is typically used for network monitoring. pass all multicast filtering mode. rmac supports the reception of only multicast frames. pass all multicast + 16 perfect filtering mode. this mode passes multicast frames and frames with addresses matching 1 of the 16 addresses in the setup frame. pass all multicast + 1 perfect filtering mode. this mode passes all multicast addresses and the single unicast address located in bytes <156, 157>, <160, 161>, <164, 165> of the setup frame. 7.8.5 receive status handling at the head of each frame received to dmac buffering is a status qword (64 bits). bits 59-32 of the status qword are the local mib counters that are maintained by the hardware. these counters (crc, aln, long, runt, and oflw) can be read by the software from the rmac receive status as listed in table 7-10. the mib values are incremented, as appropriate, for each errored packet received from the network, and inserted as part of the status qword for each good packet that causes an interrupt when received. each of the local mib counters are reset when an interrupt is generated for a good packet received. each of the mib counters will maintain a value of all one's if they overflow, and a good packet received interrupt will clear them. the contents of this status qword are shown in table 7-8.
cx82100 home network processor data sheet 7-24 conexant proprietary and confidential information 101306c table 7-8. definition of rmac receive status bit(s) default name description remarks 63-60 reserved. 59-52 0 crc no. of crc errors. the number of errors accumulated between good frames received. range = 0?255. mib counter 51-48 0 aln no. of alignment errors. the number of alignment errors accumulated between good frames. range = 0?15. mib counter 47-44 0 long no. of long packets. the number of packets >1518 bytes accumulated between good frames. range = 0?15. mib counter 43-36 0 runt no. of runt packets. the number of packets <64 bytes accumulated between good frames. range = 0?255. mib counter 35-32 0 oflw no. of overflow packets. the number of packets that caused fifo overflow accumulated between good frames. range = 0?15. mib counter 31-16 0 fl frame length. frame length in bytes including crc. range = 0?63. 15 0 es error summary. 0 = error not detected. 1 = error detected (logical or of the following: fifo overflow, crc error, late collision, packet too long, packet too short). 14 0 always 0. 13-12 0 om operating mode. 00 = normal operation. 01 = internal loopback. 10 = external loopback. 11 = reserved. 11 0 ts packet too short. 0 = packet length 64 bytes. 1 = packet length < 64 bytes. 10 0 mf multicast frame. 0 = not multicast frame. 1 = multicast frame. 9-8 0 always 0. 70 tl packet too long. 0 = packet length 1518 bytes. 1 = packet length > 1518 bytes. 60 lc late collision. 0 = collision did not occur after dmac transfer initiated. 1 = collision occurred after dmac transfer initiated. 50 oft old frame type. 0 = frame length 1500 bytes. 1 = frame length > 1500 bytes (legacy from dix support). 40 rw receive watchdog. 0 = watchdog timer expired during receipt of this packet. 1 = watchdog timer expired during receipt of this packet.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 7-25 bit(s) default name description remarks 31 always 1. 20 db dribble bit. 0 = packet length is an integer multiple of 8 bits. 1 = packet length is not an integer multiple of 8 bits. 10 ce crc error. 0 = crc error due to crc mismatch not detected. 1 = crc error due to crc mismatch detect. 00 of fifo overflow. 0 = rmac fifo did not overflow. 1 = rmac fifo overflowed.
cx82100 home network processor data sheet 7-26 conexant proprietary and confidential information 101306c 7.8.6 sequence of receiver dma operation the sequence of receiver dma operation is illustrated in figure 7-11. figure 7-11. sequence of receiver dma operation 101545_038 host specifies the circular buffer for the receiving channel {x} by loading the base pointer dmac_{x}_ptr1 and the length dmac_{x}_cnt1 host initiates the setup frame to configure the h/w address filtering. transmit & receive operations are disabled. host controls the receive start/stop by programming the e_na_sr bit of the e_na_1 or e_na_2 register rmac issues dma_save command to dmac to save dmac_{x}_cnt1 to dmac_{x}_cnt3 8 bytes of data collected? a complete frame received? yes no no yes mib counter are loaded to the status double-word which is in turn written to the head of the received frame by dmac. rmac issues dma_xnxt to dmac to transfer the data to the buffer host programs the type of address filtering in the e_na_1 or e_na_2 register (7 different types). e_na_sr=1? no yes rmac collects data bits from mii as long as the carrier sense is aserted. e_na_sr deasserted? yes no wait for e_na_sr assertion a good frame received? no rmac updates the mib counters and aborts the frame by sending dma_reld command to dmac yes rmac interrupts the host and the host processes the good frame rmac resets mib counters and the status double-word. wait for e_na_sr assertion
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 7-27 7.9 7-wire serial interface (7-ws) this mode is enabled by setting bit 7 of the emac x network access register (e_na_{x}). in this mode the mii interface works in serial mode and is designed to interface to conexant?s cx24611 homepna 2.0 phy/afe or to any other gpsi interface (amd's "general purpose serial interface," a de facto standard for mac-to- 10base-t device interface). all mii signals function the same way as in ethernet mode except that the 4-bit data is serialized on pins emx_txd0 and emx_rxd0, and emx_txd0 and emx_txen are driven from the negative edge of emx_tx_clk. table 7-9 describes the signals for the 7-ws interface. table 7-9. 7-ws interface signals 7-ws signal mii signal direction description rxd emx_rxd0 input receive data. receive input bit stream. rclk emx_rx_clk input receive clock. a 10 mhz square wave synchronized to the receive data and only active while receiving an input bit stream. rena emx_rxcrs input receive enable. a logical input that indicates the presence of carrier on the channel. txd emx_txd0 output transmit data. transmit output bit stream. tclk emx_tx_clk input transmit clock. 10 mhz clock. tena emx_txen output transmit enable. transmit output bit stream enable. while asserted, it enables valid transmit output (txd). clsn emx_col input collision. a logical input that indicates that a collision is occurring on the channel.
cx82100 home network processor data sheet 7-28 conexant proprietary and confidential information 101306c 7.10 emac register memory map emac registers are identified in table 7-10. table 7-10. emac registers register label register name asb address type default value ref. e_dma_1 emac 1 source/destination dma data register 0x00310000 rwp (don?t care) 7.11.1 e_na_1 emac 1 network access register 0x00310004 rw 0x80200000 7.11.3 e_stat_1 emac 1 status register 0x00310008 rw* 0x00000000 7.11.4 e_ie_1 emac 1 interrupt enable register 0x0031000c rw 0x00000000 7.11.6 e_lp_1 emac 1 receiver last packet register 0x00310010 rw* 0x00000000 7.11.5 e_mii_1 emac 1 mii management interface register 0x00310018 rw 1 0x00000008 7.11.7 et_dma_1 emac 1 destination dma data register 0x00310020 rop (don?t care) 7.11.2 e_dma_2 emac 2 source/destination dma data register 0x00320000 rwp (don?t care) 7.11.1 e_na_2 emac 2 network access register 0x00320004 rw 0x80200000 7.11.3 e_stat_2 emac 2 status register 0x00320008 rw* 0x00000000 7.11.4 e_ie_2 emac 2 interrupt enable register 0x0032000c rw 0x00000000 7.11.6 e_lp_2 emac 2 receiver last packet register 0x00320010 rw* 0x00000000 7.11.5 e_mii_2 emac 2 mii management interface register 0x00320018 rw 2 0x00000008 7.11.7 et_dma_2 emac 2 destination dma data register 0x00320020 rop (don?t care) 7.11.2 notes: 1. bit e_mii_1[1] is read only. 2. bit e_mii_2[1] is read only.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 7-29 7.11 emac registers 7.11.1 emac x source/destination dma data register (e_dma_1: 0x00310000 and e_dma_2: 0x00320000) e_dma_1 and e_dma_2 are the emac source/destination dma data registers for emac1 and emac2, respectively (used by the emac dma transmit channel). bit(s) type default name description 63:0 rwp 64?bx e_dma a qword buffer for dma source/destination access. 7.11.2 emac x destination dma data register (et_dma_1: 0x00310020 and et_dma_2: 0x00320020) et_dma_1 and et_dma_2 are the emac destination dma data registers for emac1 and emac2, respectively (used by the emac dma receive channel). bit(s) type default name description 63:0 rop 64?bx et_dma a qword buffer for dma destination access.
cx82100 home network processor data sheet 7-30 conexant proprietary and confidential information 101306c 7.11.3 emac x network access register (e_na_1: 0x00310004 and e_na_2: 0x00320004) e_na_1 and e_na_2 are the emac network access registers for emac1 and emac2, respectively. bit(s) type default name description 31 rw 1?b1 e_na_rtx tx software reset. 0 = no effect. 1 = once 1 is written, write 0 into field to get out of reset. all internal registers of rx and tx (including all bits of this register) are reset to their default value. 30 rw 1?b0 e_na_stop stop transmit control. 0 = no effect. 1 = stop the transmitter after the current frame (if any). 29:28 unused. 27 rw 1?b0 e_na_hp hash/perfect address filter mode control. e_na_hp, e_na_ho, e_na_if, e_na_pr, e_na_pm should be programmed according to table 7-7 to select the desired address filtering mode. 26 rw 1?b0 e_na_ho hash only control. see e_na_hp for description. 25 rw 1?b0 e_na_if inverse filter control. see e_na_hp for description. 24 rw 1?b0 e_na_pr promiscuous mode control. see e_na_hp for description. 23 rw 1?b0 e_na_pm pass all multicast. see e_na_hp for description. 22 rw 1?b0 e_na_pb pass bad packet control. 0 = disable. 1 = receive any packets, if pass address filter, including runt packets, crc error, truncated packets. 21 rw 1?b1 e_na_rrx rx software reset. 0 = no effect. 1 = once 1 is written, write 0 into field to get out of reset. all internal rx registers are reset to their default value. this bit can only be cleared after e_na_rtx bit is cleared. 20 rw 1?b0 e_na_thu tx test huj control. 19 rw 1?b0 e_na_dis tx disable back-off counter control. 18 rw 1?b0 e_na_rut tx reset unit timer control. 17:16 rw 2?b00 e_na_ifg interframe gap (ifg) period select. value is read as an integer and substitutes e_na_ifg in the following equations: 100 mbps: ifg = 960 ? 40* e_na_ifg ns 10 mbps: ifg = 9600 ? 40* e_na_ifg ns
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 7-31 bit(s) type default name description 15 rw 1?b0 e_na_jbd jabber disable. 0 = enable. 1 = disable checking for exceedingly long packets during transmit operations. if the transmit jabber function is enabled, e_s_tjt will be set after the timer has expired. e_na_jclk controls the duration of the transmit jabber time-out clock. 14 rw 1?b0 e_na_huj host un-jabber control. this field configures the time delay between a transmit jabber time- out event and re-enabling the transmit process. 0 = 420 ms/42 ms. 1 = immediate. the bit-time is dependent on the current network operating speed. 13 rw 1?b0 e_na_jclk jabber clock control. this field is used to configure the length of the timer used to detect transmit jabber conditions and cut-off transmission. 0 = 26 ms/2.6 ms. 1 = 2560 bit-times. 12 rw 1?b0 e_na_sb start/stop backoff counter. 0 = incrementing of the collision backoff counter is not stopped while carrier sense is true. 1 = incrementing of the collision backoff counter is stopped while carrier sense is true. once carrier sense is false, the counter will resume incrementing. valid only in half-duplex mode. if this field is cleared, the collision backoff counter may expire while carrier sense is true. since carrier sense is an indication of network activity, the hnp may attempt to transmit and have to defer. 11 rw 1?b0 e_na_fd full-duplex select. 0 = configure for half-duplex operation. 1 = configure for full-duplex operation. 10:9 rw 2?b00 e_na_om operating mode select. configures the device for normal operation or loopback test modes. 00 = normal operation. 10 = external loopback test. 01 = internal loopback test. 11 = reserved. 8rw 1?b0 e_na_fc tx force collisions. 0 = do not force collisions on each transmit attempt while in internal loopback mode. 1 = force collisions on each transmit attempt while in internal loopback mode. 7 rw 1?b0 e_na_hlan 7-ws enable. 0 = enable parallel data mode on mii pins. 1 = enable 7-wire serial interface (7-ws) on mii pins. 6 rw 1?b0 e_na_sr receive start/stop control. 1 = start receive. 0 = stop receive. 5rw 1?b0 e_na_ns network speed select. 0 = configure 100 mbps network speed. 1 = configure 10 mbps network speed. 4rw 1?b0 e_na_rwr receive watchdog release time select. 0 = release watchdog timer 24 bit times after carrier is deasserted. 1 = release watchdog timer 48 bit times after carrier is deasserted.
cx82100 home network processor data sheet 7-32 conexant proprietary and confidential information 101306c bit(s) type default name description 3rw 1?b0 e_na_rwd receive watchdog disable. 0 = if the receiving packet's length is longer than 2560 bytes, the watchdog timer will be expired. 1 = disable the watchdog timer. 2:1 reserved. 0rw 1?b0 e_na_strt start transmit control. 0 = no effect (this bit is self-clearing). 1 = writing a 1 causes the transmitter to start if the transmitter was idle and the stop bit (e_na_stop) is 0. e_na_stop (bit 30) overrides e_na_strt. this bit is auto-cleared after tx is complete whether it was successful or not. e_na_strt e_na_stop description 0 0 = do nothing 1 0 = start transmitter x 1 = stop transmitter
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 7-33 7.11.4 emac x status register (e_stat_1: 0x00310008 and e_stat_2: 0x00320008) e_stat_1 and e_stat_2 are the emac status registers for emac1 and emac2, respectively. writing to this register will clear all of its bits (as denoted by rw*). bit(s) type default name description 31 rw* 1?b0 e_s_tu transmit stopped. 0 = descriptor ready. 1 = descriptor not ready. 30:27 rw* 4?b0 e_s_rs receive state. indicates the receiver mii state (for test only). 26 rw* 1?b0 e_s_ro receive fifo overflow. 0 = receive fifo has not overflowed. 1 = receive fifo has overflowed. 25 rw* 1?b0 e_s_rwt receive watchdog time-out. 0 = receive watchdog timer has not expired. 1 = receive watchdog timer has not expired (based on lan_wtr). 24:21 rw* 4?b0 e_s_tds transmit buffer manager state. for test only. 20:17 rw* 4?b0 e_s_ts transmit state. indicates the transmitter state (except during setup frames). for test only. 16 rw* 1?b0 e_s_tof transmit fifo overflow. 0 = transmit fifo has not overflowed. 1 = transmit fifo has overflowed. 15 rw* 1?b0 e_s_tuf transmit fifo underflow. 0 = transmit fifo has not underflowed. 1 = transmit fifo has underflowed. 14 rw* 1?b0 e_s_ed excessive transmit deferrals. 0 = deferred longer than 10 mbps (8192 x 400 ns) while attempting to transmit. 1 = deferred longer than 100 mbps (81920 x 40 ns) while attempting to transmit. 13 rw* 1?b0 e_s_df deferred frame. 0 = current transmit frame has not been deferred at least once. 1 = current transmit frame has been deferred at least once. 12 rw* 1?b0 e_s_cd carrier done. 0 = frame transmit not done from mii interface. 1 = frame transmit done from mii interface. 11 rw* 1?b0 e_s_es transmitter error summary. 0 = none of the bits indicated by the 1 state are set. 1 = any of the following transmit error status bits are set to a 1: transmit fault (e_s_tf), 16+ collisions (e_s_16), late collision (e_s_lc), no carrier (e_s_ncrs), lost carrier (e_s_lcrs), or transmit jabber timeout (e_s_tjt). 10 rw* 1?b0 e_s_rld reload abort. 0 = transmit fifo reload/abort has not occurred during current frame (includes collisions). 1 = transmit fifo reload/abort has occurred during current frame (includes collisions).
cx82100 home network processor data sheet 7-34 conexant proprietary and confidential information 101306c bit(s) type default name description 9 rw* 1?b0 e_s_tf transmit fault. 0 = unexpected transmit data request has not occurred during current frame. 1 = unexpected transmit data request has occurred during current frame. 8 rw* 1?b0 e_s_tjt transmit jabber timeout. 0 = jabber timer has not expired. 1 = jabber timer has expired. e_na_huj and e_na_huj must be configured for this bit to function. 7 rw* 1?b0 e_s_ncrs no carrier. 0 = carrier detected. 1 = no carrier (emx_crs pin never transitioned high) during frame transmit. 6 rw* 1?b0 e_s_lcrs lost carrier. 0 = carrier was not lost during frame transmit. 1 = carrier was lost (emx_crs pin transitioned low) at least once frame transmit. 5 rw* 1?b0 e_s_16 16+ collisions. 0 = 16 or more collisions have not occurred during frame transmit. 1 = 16 or more collisions have occurred during frame transmit. 4 rw* 1?b0 e_s_lc late collision. 0 = a late collision (after the 64th byte) has not occurred during frame transmit. 1 = a late collision (after the 64th byte) has occurred during frame transmit (mib16). 3:0 rw* 4?b0 e_s_cc collision count. transmit collision count of the current frame. resets after the frame is transmitted. increments with every collision of the current frame. 7.11.5 emac x receiver last packet register (e_lp_1: 0x00310010 and e_lp_2: 0x00320010) e_lp_1 and e_lp_2 are the emac receiver last packet registers for emac1 and emac2, respectively. writing to this register will clear all of its bits (as denoted by rw*). bit(s) type default name description 31:10 reserved. 9:6 rw* 4?b0 e_lp_rdma receive dma state machine state. (for test only.) 5:2 rw* 4?b0 e_lp_rfifo receive fifo state machine state. (for test only.) 1 rw* 1?b0 e_lp_ri receive done ok from rx buffer manager. 0 rw* 1?b0 e_lp_ti transmit done ok from tx buffer manager.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 7-35 7.11.6 emac x interrupt enable register (e_ie_1: 0x0031000c and e_ie_2: 0x0032000c) e_ie_1 and e_ie_2 are the emac error interrupt enable registers for emac1 and emac2, respectively. bit(s) type default name description 31:17 reserved. 16 rw 1?b0 e_ie_ni normal interrupt summary enable. masks e_lp_ti or e_lp_ri (1 = enable; 0 = disable). 15 rw 1?b0 e_ie_rw receive watchdog timer interrupt enable. masks e_s_rwt (1 = enable; 0 = disable). 14 rw 1?b0 e_ie_ri receive ok interrupt enable. masks e_lp_ri (1 = enable; 0 = disable). 13 rw 1?b0 e_ie_ai abnormal interrupt summary enable. masks e_s_es or e_s_tuf or e_s_tof or e_s_ro or e_s_tjt or e_s_rwt (1 = enable; 0 = disable). 12 rw 1?b0 e_ie_lc late collision interrupt enable. masks e_s_lc (1 = enable; 0 = disable). 11 rw 1?b0 e_ie_16 16 collisions interrupt enable. masks e_s_16 (1 = enable; 0 = disable). 10 rw 1?b0 e_ie_lcrs lost carrier interrupt enable. masks e_s_lcrs (1 = enable; 0 = disable). 9 rw 1?b0 e_ie_ncrs no carrier interrupt enable. masks e_s_ncrs (1 = enable; 0 = disable). 8rw 1?b0 e_ie_tf transmit fault interrupt enable. masks e_s_tf (1 = enable; 0 = disable). 7rw 1?b0 e_ie_rld transmit reload/abort interrupt enable. masks e_s_rld (1 = enable; 0 = disable). 6 rw 1?b0 e_ie_ed excessive deferral interrupt enable. masks e_s_ed (1 = enable; 0 = disable). 5rw 1?b0 e_ie_df transmit deferred interrupt enable. masks e_s_df (1 = enable; 0 = disable). 4rw 1?b0 e_ie_tof transmit overflow interrupt enable. masks e_s_tof (1 = enable; 0 = disable). 3rw 1?b0 e_ie_tuf transmit underflow interrupt enable. masks e_s_tuf (1 = enable; 0 = disable). 2rw 1?b0 e_ie_tjt transmit jabber time-out interrupt enable. masks e_s_tjt (1 = enable; 0 = disable). 1rw 1?b0 e_ie_tu transmit stopped interrupt enable. masks e_s_tu (1 = enable; 0 = disable). 0rw 1?b0 e_ie_ti transmit ok interrupt enable. masks e_lp_ti (1 = enable; 0 = disable).
cx82100 home network processor data sheet 7-36 conexant proprietary and confidential information 101306c 7.11.7 emac x mii management interface register (e_mii_1: 0x00310018 and e_mii_2: 0x00320018) e_mii_1 and e_mii_2 are the emac mii management interface registers for emac1 and emac2, respectively. bit(s) type default name description 31:5 reserved. 4rw 1?b0 e_mdip active edge of emx_mdc pin in input mode. 0 = emx_mdio is sampled on the falling edge of emx_mdc. 1 = emx_mdio is sampled on the rising edge of emx_mdc. 3rw 1?b1 e_mm direction of signal on emx_mdio pin. 0 = emx_mdio pin is an output. 1 = emx_mdio pin is an input. 2rw 1?b0 e_mdo value driven on emx_mdio pin. 0 = drive emx_mdio pin low when e_mm = 0 (output mode). 1 = drive emx_mdio pin high when e_mm = 0 (output mode). 1ro 1?b0e_mdi value read on emx_mdio pin. 0 = emx_mdio pin is low when e_mm = 1 (input mode). 1 = emx_mdio pin is high when e_mm = 1 (input mode). 0rw 1?b0 e_mdc value driven on emx_mdc pin. 0 = drive emx_mdc pin low. 1 = drive emx_mdc pin high.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 8-1 8 usb interface description the usb interface (or udc core) consists of three major functions: usb controller (usbc), apb/dma interface (i/f), and usb differential transceiver (figure 8-1). the usbc includes the following functions: ? phase locked loop (pll) block. the pll block extracts the usb clock and data from the usb cable. the input to the pll block comes from an usb differential transceiver. the pll runs on a 48 mhz clock. the pll also generates a 12 mhz clock from the 48 mhz clock and supplies it to the serial interface engine (sie) and usb bridge layer (ubl) blocks. the pll identifies the single ended zero (se0) signal on the usb and sends it to the sie block. ? serial interface engine (sie) block. the sie block performs the front end functions of the usb protocol such as syncfield identification, nrzi-nrz conversion, token packet decoding, bit stripping, bit stuffing, nrz-nrzi conversion, crc5 checking, and crc16 generation and checking. the sie also converts the serial packet to 8-bit parallel data. the sie block has a 1-byte buffer for buffering the data during data transmission and reception. ? usb bridge layer (ubl) block. the ubl block handles the error recovery mechanism during transactions while interfacing to the application (the application includes the apb/dma i/f, the arm940t processor, and the arm firmware processing the data). the ubl also decodes and handles all the standard control transfers addressed to endpoint zero. the ubl passes some usb commands onto the apb/dma i/f so that the application can decode and process the command. the ubl block has two sub-blocks called the protocol layer (pl) block and the endpoint (ep) block. the pl block controls the sie block by providing necessary handshake signals to the sie and communicates with the apb/dma i/f. it also performs error recovery if the apb/dma i/f violates the data transfer protocol. the ep block handles all the control transfers to endpoint zero. the ep block decodes and responds to all the usb standard commands and some other usb commands (e.g., get descriptor) to the apb/dma i/f. the ep block maintains the buffer for device address, buffer for storing the present active configuration, and the logic to determine the present state of the device (usbc). ? endpoint information (epinfo) block : the epinfo maintains the registers that store information about the endpoints. the epinfo also stores the information about the size of configuration in the usbc. the information about the current endpoint is multiplexed from these registers and is provided to the pl block which controls the sie block based on this information. the epinfo also includes the data0/data1 synchronization bits for each bidirectional endpoint the usbc supports. also, the epinfo includes the endptstalled bit for each of the supported logical endpoints to indicate the stalled status of the endpoint. the hnp epinfo supports up to 3 active bidirectional logical endpoints and one interrupt endpoint. the endpoint number ranges from 0 to 4.
cx82100 home network processor data sheet 8-2 conexant proprietary and confidential information 101306c figure 8-1. block diagram of the usb interface 101545_054 protocol layer (pl) block endpoint (ep) block endpoint inform ation (epinfo) block usb bridge layer (ubl) block transmitter receiver serial interface (sie) block sync pll usb differential transceiver usb controller (usbc) usb apb/dma interface (i/f) apb usb interface (udc core) hnp
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 8-3 8.1 udc data path the udc data path supports usb transmit and receive data. 8.1.1 usb transmit data path (endpoint in channel) the usb transmit data flow is illustrated in figure 8-2. figure 8-2. usb transmit data flow 101545_055 data buffer ubl from apb/ dma i/f handshake generator data + crc16 m u x token assembly bit stuffing nrz-to-nrzi conversion to usb differential transceiver crc16 data payload ack, nak, stall in, out, sof, setup complete packet 01 0 1 0 1 111 0 1 1 1 11 bit stuffing nrz nrzi + - nrz to nrzi conversion 0 = inverting the polarity of the output signal 1 = not inverting the output signal
cx82100 home network processor data sheet 8-4 conexant proprietary and confidential information 101306c 8.1.2 usb receive data path (endpoint out channel) the usb receive data flow is illustrated in figure 8-3. figure 8-3. usb receive data flow 101545_056 data buffer ubl to apb/ dma i/f address checker data/crc checker nrzi-to- nrz conversion sync field indentification pll from usb differential transceiver pid decode handshake checker serial-to- parallel conversion 00 0 0 0 0 01 nrzi data pid0 pid2 pid1 sync pattern
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 8-5 8.2 usb data flow usb data can be identified as control, bulk, or interrupt data in the hnp. control data is usually structured as a command phase initiated by the usb host, followed by data either provided by the device (in), i.e., hnp (in), or sent to it by the host (out), followed in turn by a status phase which serves as an acknowledgement of transfer. control transfers are directed to endpoint 0, and requires no device configuration, i.e., control transfers can be active from the moment of device attachment. all other transfers require device configuration and setting of the appropriate device address by the host to be accepted by the hnp. in another words, a process called enumeration is must be initiated by the host every time the hnp is connected. control data flow through endpoint 0 must be usb specification rev. 1.1 chapter 9 compliant and other usb stack command aware. packet size for endpoint 0 is 64 bytes for control data and 8 bytes for control command. bulk transfers are simple data transfers with ack/nak token exchange between the host and the hnp to signal the completion of the transfer. again, these transfers are started by the host sending a in (out) token to the hnp, which responds within a timeout period with data and/or ack/nak (depending on the direction of transfer) to keep the host from retrying to transfer the data. the packet size for bulk transfers is always less than or equal to 64 bytes. interrupt data is infrequent data that flows only from the hnp to the host and is a result of the host polling the hnp periodically. the hnp interrupt endpoint is fixed at in type with 8 bytes per packet.
cx82100 home network processor data sheet 8-6 conexant proprietary and confidential information 101306c 8.3 udc core the usb core includes the endpoint buffers and associated processing. 8.3.1 endpoint buffer format the udc stores all the endpoint configuration information for each endpoint that the hnp supports. each endpoint configuration is stored in a separate buffer called endptbuf. the udc core has defined the logical and physical endpoints for its implementation. a ?logical endpoint? is an endpoint that is visible to the host. generally, for usb, there are 16 logical endpoints from the host?s perspective (endpoint 0 to endpoint 15). at any time the host can access one of these logical endpoints. a ?physical endpoint?, on the other hand, is the actual unidirectional endpoint that is implemented in the hardware. two physical endpoints can be paired to form a bidirectional endpoint sharing the same logical endpoint number. the udc supports one configuration, one interface, no alternate interface, three bidirectional endpoints plus one interrupt endpoint (seven physical endpoints total). since each endpoint requires 5 bytes for its endpoint configuration, then the total number of endpoint configuration bytes allocated within the udc core are (5 * 7) + 5 (endpoint 0). firmware initializes these endptbuf configuration bytes upon por or hardware reset event. please refer to section 8.3.3 for the procedure to initialize these endpoint buffer configurations. table 8-1. endpoint buffer format in udc core bit(s) type description 39:36 ep_num logical endpoint number. 35:34 ep_config configuration number. only configuration 1 is supported. 33:32 ep_interface interface number. three interfaces (0, 1, or 2) are supported. 31:29 ep_altsetting alternate setting. only alternate setting 0 for each interface is supported. 28:27 ep_type type of endpoint. 00 = control. 01 = isochronous. 10 = bulk. 11 = interrupt. 26 ep_dir direction of data flow. 0 = out. 1 = in. this bit is ignored for control endpoints. 25:16 ep_maxpktsize maximum packet size for this endpoint. 15:0 ep_bufadrptr address pointer for the associated endpoint. only bits [3:0] are used. this must match with the pointer specified in u_ctr2 register for transfer to take place. it is always zero for endpoint 0.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 8-7 8.3.2 example of endpoint buffer encoding as shown in figure 8-4, the hnp supports one configuration, one interface with no alternate setting and four logical endpoints (endpoints 1, 2, 3, and 4). the first three endpoints are bidirectional endpoints and the fourth is an interrupt endpoint, therefore there are nine physical endpoints total (including controlled endpoint 0). in the udc, one endptbuf (endpoint buffer) is associated with each physical endpoint. hence, there are eight endptbufs in the udc for the configuration shown in figure 8-4. endpoint 0 needs only one endptbuf, although it is bidirectional. an example of the encoding of the endptbuf is shown in table 8-2. except for interrupt endpoint?s packet size being fixed at 8 bytes, other endpoints? packet size must be less than or equal to 64 bytes. figure 8-4. example of an usb device for hnp 101545_057 configuration 1 interface 0 alt setting 0 logical no. physical no. ep 0 1 control ep 1 2 bulk-in ep 1 3 bulk-out ep 2 4 bulk-in ep 2 5 bulk-out ep 3 6 bulk-in ep 3 7 bulk-out ep 4 8 interrupt table 8-2. example of the endptbuf encoding endptbuf no. 39:36 35:34 33:32 31:29 28:27 26 25:16 15:0 1 0000 01 00 000 00 0 00 0100 0000 0000 0000 0000 0000 2 0001 01 00 000 10 0 00 0100 0000 0000 0000 0000 0001 3 0001 01 00 000 10 1 00 0100 0000 0000 0000 0000 0001 4 0010 01 00 000 10 0 00 0100 0000 0000 0000 0000 0001 5 0010 01 00 000 10 1 00 0100 0000 0000 0000 0000 0010 6 0011 01 00 000 10 0 00 0100 0000 0000 0000 0000 0011 7 0011 01 00 000 10 1 00 0100 0000 0000 0000 0000 0011 8 0100 01 00 000 11 1 00 0001 0100 0000 0000 0000 0100
cx82100 home network processor data sheet 8-8 conexant proprietary and confidential information 101306c 8.3.3 loading of the endptbuf configurations the endpoint configuration in the udc core is accomplished by writing to the u_cfg register the same byte-wise data that the udc core expects. the target of these configuration writes are the endpoint buffers which have the format shown in table 8-1. starting from the endpoint 0 descriptor (endptbuf0), the configuration data is written to endptbuf0[39:32], followed by endptbuf0[31:24], and so on (endptbuf0 is reserved for endpoint 0). once the 5-byte endptbuf0 has been filled, endptbuf1, and the others are filled in order, most significant byte first. since the register writes from apb are 4 bytes in length, the data is grouped so that the first byte to the udc interface comes from the least significant byte of the register u_cfg. after the contents of the register write have been passed on to the udc core, the firmware is requested, via the cfgnext_int flag in the u_stat register, to write the next 4 bytes of configuration data. this continues until the endpoint descriptors have been updated, with the assertion of cfgdn_int status. during configuration, the cfg_en control bit is set to prevent any data from being transferred to erroneous addresses. once the configuration data has been loaded, the cfg_en bit is reset and endpoints are enabled through the setting of their enable bits in the u_ctr1 register. prior to enabling the endpoints, the endpoint addresses in the u_ctr2 register must be programmed to match those passed to the endpoint descriptors ep_bufadrptr parameters in the endptbuf. usb global en bit (bit0 of u_ctr1) can only set once per por or hardware reset event, after that the udc core will accept the endpoint configuration data as described in the sequences above. usb reset bit (bit 30 of u_ctr1) can be used to reset the udc core the same way as por or a hardware reset event. figure 8-5 shows the example of loading the endptbuf configurations described in table 8-2.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 8-9 figure 8-5. loading of the endptbuf configurations b#7 b#6 b#5 b#4 b#3 b#2 b#1 b#0 b#14 b#13 b#12 b#11 b#10 b#9 b#8 b#39 b#38 b#37 b#36 .... .... .... b#35 .... .... b#3 b#2 b#1 b#0 101545_058 39:32 31:24 7:0 15:8 23:16 endptbuf0 endptbuf1 endptbuf4 endptbuf3 endptbuf2 u_cfg register 31:24 7:0 15:8 23:16 apb bytelane 0 apb bytelane 3 apb bytelane 2 apb bytelane 1 b#0 b#3 b#2 b#1 to usb interface block b#7 b#6 b#5 b#4 b#3 b#2 b#1 b#0 b#15 b#14 b#13 b#12 b#11 b#10 b#9 b#8 b#19 b#18 b#17 b#16 b#39 b#38 b#37 b#36 .... .... .... .... 8.3.4 usb command handling the udc handles and decodes all usb standard commands defined in the usb specification rev. 1.1. the udc returns a stall handshake if it receives an unsupported or invalid standard command. the udc will forward all controlled commands (endpoint 0), as well as other endpoint out data, to the application via a dma rx buffer except the following controlled commands which are decoded internally: ? clear feature ? get configuration ? get interface ? get status ? set address ? set configuration ? set feature ? set interface
cx82100 home network processor data sheet 8-10 conexant proprietary and confidential information 101306c 8.4 usb dma interface dmac interfaces with the usb device through addressed writes/reads that conform to the common dma protocol. 8.4.1 dma receive channel the dma channel supporting receive out endpoints is illustrated in figure 8-6. the endpoint data is described in table 8-3. figure 8-6. dma channel supporting usb receive out endpoints 101545_059 arm host dmac usb device dma ch 12 dma ch 12 ep0_out endpoints ep3_out ep2_out ep1_out table 8-3. dma channel supporting usb receive out endpoints endpoint no. direction name dma channel description endpoint 0 out ep0_out 12 usb specification chapter 9 compliance and other usb stack aware commands. maximum packet size is 64 bytes. endpoint 1 out ep1_out 12 bulk out data. maximum packet size is 64 bytes. endpoint 2 out ep2_out 12 bulk out data. maximum packet size is 64 bytes. endpoint 3 out ep3_out 12 bulk out data. maximum packet size is 64 bytes. whenever the host sends a control/data packet that is forwarded by the hnp, the data is then organized in 8-byte qword segments by the udc core and written to a circular dma rx buffer (the pointer and buffer length has been initialized for dma channel 12 operation by the firmware). each forwarded packet consists of an 8-byte status header followed by packet control/data payload arranged in little endian byte order. the exact number of bytes of the received data/control packet is specified in the count parameter of the status header. in case of a transaction having a non-integer of qword boundary, the last qword in the usb rx buffer segment holding that packet?s data is zero-padded in higher order locations. firmware also keeps track of the next packet pointer location in the circular dma rx buffer. the status header is defined in table 8-4.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 8-11 table 8-4. status qword for receive (out) endpoint apb buffers bit(s) default name description 63:16 0 reserved. 15 0 pkt_in packet has been received without errors. 14:12 0 reserved. 11:8 0 ep_num endpoint address pointer that received this packet. 7 0 setup current packet is a setup packet. 6:0 0 count count of data bytes received in this packet. after the dma channel 12 pointer and counter (circular rx dma buffer) and ep_out_rx_bufsize register are initialized, the rv_init bit in u_ctr1 register is set and cleared (in the next instruction) before enabling endpoint out operation. this bit is not set again until new rx dma buffer setting is required and only when all receive endpoints have been disabled. data transfer from the host to the hnp commences if there is space in the rx dma buffer, and continues until the rx dma buffer is full. requests to dmac are generated whenever there is data in the rx fifo of a given endpoint, and usb ack has not been received. upon reception of usb ack, data is flushed into the rx dma buffer, a qword status header is written to the beginning of the buffer, and the ep_out_rx_pend register is increased by one. simultaneously, a status bit (ep0o_int, ep1o_int, ep2o_int, or ep3o_int) is set in the u_stat register confirming the successful reception of data on that endpoint. a rx dma interrupt request is forwarded to the interrupt controller if the interrupt is enabled and also if trigger conditions are satisfied. interrupt events can be set from a variety of interrupt sources: single packet completion, multiple packet completion, and/or packet pending receive watchdog timeout. the firmware parses the endpoint information from the status header and acts accordingly. when any number of rx packets are safely processed by firmware, then the same number is written to the ep_out_rx_dec register so the udc core can reuse the packets? dma buffers. there will be no new packets transferred to the rx dma buffer if ep_out_rx_pend = ep_out_rx_bufsize which also triggers an rx dma overrun condition. the usb rx dma logic always initializes the next dma status header packet with 0 after the first rx packet is received from the host. this can cause a problem if rx dma overrun condition happens (rx dma buffer full with all 64 bytes packet size) due to firmware overhead and system latency. thus, it may be necessary to increase the hardware buffer size by 8 bytes so that the most recent unprocessed status header content is still intact if when overrun does occur. note that dmac channel 12 count register should be limited to 16376 bytes due to restriction of dmac count register. since the maximum hardware rx dma buffer for each data packet is 72 bytes (64 bytes of data and 8 bytes of status header). with a given dma rx buffer size in bytes, the value programmed into the following registers should be: dmac_12_cnt1 = (dma rx buffer size) / 8 ep_out_rx_bufsize = ((dma rx buffer size) / 72) - 1
cx82100 home network processor data sheet 8-12 conexant proprietary and confidential information 101306c 8.4.2 dma transmit channel the dma channels supporting usb transmit in endpoints are illustrated in figure 8-6. the endpoint data is described in table 8-3. figure 8-7. dma channels for usb transmit in endpoints 101545_060 arm host dmac endpoints usb device ep0_in (ch 13) ep1_in (ch 11) ep3_in (ch 9) ep2_in (ch 10) dma ch 10 dma ch 11 dma ch 13 dma ch 9 dma ch 10 dma ch 11 dma ch 13 dma ch 9 table 8-5. dma channels for usb transmit in endpoints endpoint no. direction name dma channel description endpoint 0 in ep0_in 13 control data. maximum packet size is 64 bytes. endpoint 1 in ep1_in 11 bulk in data. maximum packet size is 64 bytes. endpoint 2 in ep2_in 10 bulk in data. maximum packet size is 64 bytes. endpoint 3 in ep3_in 9 bulk in data. maximum packet size is 64 bytes. the firmware sets up all four in endpoint (endpoint0 ? endpoint3) tx dma embedded link-list circular buffers associated with dmac dma channels separately. the apb/dma i/f then obtains and sends endpoint data from these linked-list buffers to the udc core in response to host requests. each individual tx dma packet buffer consists of a qword descriptor + status header followed by 64 bytes of data payload and qword embedded link-list pointer/counter pointed to next packet buffer. after setting up the proper dma buffer associated with particular endpoint and resetting the proper epx_in_dma_reset bit in u_ctr1 register, the firmware activates the endpoint, optionally enables endpoint interrupt, and is then ready for data transfer. once an endpoint data is ready, the firmware puts proper endpoint description (table 8-6) and data payload (up to 64 bytes) into corresponding the tx dma packet buffer at the current dma pointer.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 8-13 the descriptor also contains the count of bytes to be sent in the current packet and the logical endpoint address corresponding to that endpoint. if there is a mismatch between the endpoint address from the buffer descriptor and the corresponding endpoint descriptor in udc core, the "invalid header" status bit epxi_invldhdr_int is set and transfer is aborted. similar action happens if the count of bytes in the current packet is more than 64. the firmware maintains a dma pointer of current tx dma packet buffer for each endpoint. firmware then updates the epx_in_tx_inc register with the number of added data packets. apb/dma i/f logic then transfers the data out from tx dma buffer into the endpoint tx fifo buffer. when the usb host sends a request for either bulk data or control data, then udc responds with the data from the tx fifo if it has anything to transmit and continues fetching data from tx dma buffer if needed, or sends a nak if data is unavailable. when data is available, upon receiving an ack, the status (table 8-7) is updated with xmit_done bit and the requested logical ep_num number, also epx_in_tx_pend register is updated and reflecting current pending packets. the corresponding endpoint interrupt is triggered, if enabled, and if all conditions are satisfied. if the transfer is naked or an error happens during transmission, the current packet data for that endpoint is resent. on each consecutive naks from usb host, the endpoint retry counter is increased by one. after a number of unsuccessful retries (the number programmed in the epxi_errcnt bits in u_ctr3 register), an error status bit epxi_errcnt_int is set in the u_stat register. table 8-6. descriptor qword for transmit (in) endpoint tx dma packet buffer bit(s) default name description 63:16 0 reserved. 15 0 rdy buffer is ready with the entire packet to be transmitted. 14:12 0 reserved. 11:8 0 ep_num endpoint address pointer this packet transmits on. 7 0 reserved. 6:0 0 count count of data bytes to be transmitted in this packet. table 8-7. status qword for transmit (in) endpoint tx dma packet buffer bit(s) default name description 63:24 0 reserved. 23 0 xmt_done transmission of data from current buffer complete. 22:20 0 reserved. 19:16 0 ep_num endpoint address pointer this packet transmits on. 15:0 0 reserved.
cx82100 home network processor data sheet 8-14 conexant proprietary and confidential information 101306c 8.5 interrupt endpoint the interrupt endpoint is different from the other endpoints in that it does not get its data from the tx dma buffers or there is no tx dma channel available for interrupt endpoint. the interrupt endpoint relies on firmware writes to the u_idat register for the interrupt data. two writes to u_idat are required to furnish the 8 bytes of data for each interrupt packet. after the first 4 bytes have been processed, a status bit intrnext_int in u_stat is set to indicate that the firmware can now write the next 4 bytes to u_idat. an intrdn_int status is set upon completion of the data transfer to the host. 8.6 summary of the endpoints the udc endpoints are summarized in table 8-8. table 8-8. udc endpoints udc logical endpoint no. udc physical endpoint no. direction transfer type endpoint 0 1 in control endpoint 0 2 out control endpoint 1 3 in bulk endpoint 1 4 out bulk endpoint 2 5 in bulk endpoint 2 6 out bulk endpoint 3 7 in bulk endpoint 3 8 out bulk endpoint 4 9 in interrupt
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 8-15 8.7 usb register memory map usb registers are identified in table 8-9. table 8-9. usb registers register label register name asb address type default value ref. u0_dma usb source/destination dma data register 0 0x00330000 rwp (don?t care) 8.8.1 u1_dma usb source/destination dma data register 1 0x00330008 rwp (don?t care) 8.8.2 u2_dma usb source/destination dma data register 2 0x00330010 rwp (don?t care) 8.8.3 u3_dma usb source/destination dma data register 3 0x00330018 rwp (don?t care) 8.8.4 ut_dma usb destination dma data register 0x00330020 ro (don?t care) 8.8.5 u_cfg usb configuration data register 0x00330024 rw 0x00000000 8.8.6 u_idat usb interrupt data register 0x00330028 rw 0x00000000 8.8.7 u_ctr1 usb control register 1 0x0033002c rw 0x04000000 8.8.8 u_ctr2 usb control register 2 0x00330030 rw 0x00000000 8.8.9 u_ctr3 usb control register 3 0x00330034 rw 0x00000000 8.8.10 u_stat usb status 0x00330038 rr 0x00000000 8.8.11 u_ier usb interrupt enable register 0x0033003c rw 0x00000000 8.8.12 u_stat2 usb status register 2 0x00330040 rr 0x00000000 8.8.13 u_ier2 usb interrupt enable register 2 0x00330044 rw 0x00000000 8.8.14 ep0_in_tx_inc ep0_in transmit increment register 0x00330048 rw 0x00000000 8.9.1 ep0_in_tx_pend ep0_in transmit pending register 0x0033004c ro 0x00000000 8.9.2 ep0_in_tx_qwcnt ep0_in transmit qword count register 0x00330050 ro 0x00000000 8.9.3 ep1_in_tx_inc ep1_in transmit increment register 0x00330054 rw 0x00000000 8.9.4 ep1_in_tx_pend ep1_in transmit pending register 0x00330058 ro 0x00000000 8.9.5 ep1_in_tx_qwcnt ep1_in transmit qword count register 0x0033005c ro 0x00000000 8.9.6 ep2_in_tx_inc ep2_in transmit increment register 0x00330060 rw 0x00000000 8.9.7 ep2_in_tx_pend ep2_in transmit pending register 0x00330064 ro 0x00000000 8.9.8 ep2_in_tx_qwcnt ep2_in transmit qword count register 0x00330068 ro 0x00000000 8.9.9 ep3_in_tx_inc ep3_in transmit increment register 0x0033006c rw 0x00000000 8.9.10 ep3_in_tx_pend ep3_in transmit pending register 0x00330070 ro 0x00000000 8.9.11 ep3_in_tx_qwcnt ep3_in transmit qword count register 0x00330074 ro 0x00000000 8.9.12 ep_out_rx_dec ep_out receive decrement register 0x00330078 rw 0x00000000 8.9.13 ep_out_rx_pend ep_out receive pending register 0x0033007c ro 0x00000000 8.9.14 ep_out_rx_qwcnt ep_out receive qword count register 0x00330080 ro 0x00000000 8.9.16 ep_out_rx_bufsize ep_out receive buffer size register 0x00330084 rw 0x00000000 8.9.15 u_csr usb control-status register 0x00330088 ro/wo 0x00000000 8.9.20 udc_tsr udc time stamp register 0x0033008c ro 0x00000000 8.8.15 udc_stat udc status register 0x00330090 ro 0x00000000 8.8.16 usb_rxtimer usb receive dma watchdog timer register 0x00330094 rw 0x00000000 8.9.17 usb_rxtimercnt usb receive dma watchdog timer counter register 0x00330098 ro 0x00000000 8.9.18 ep_out_rx_pendlevel ep_out receive pending interrupt level register 0x0033009c rw 0x00000000 8.9.19
cx82100 home network processor data sheet 8-16 conexant proprietary and confidential information 101306c 8.8 usb registers 8.8.1 usb source/destination dma data register 0 (u0_dma: 0x00330000) u0_dma is the usb source/destination dma data register (used by dma transmit channel 13 hardware for usb endpoint 0 in channel). not used by firmware. bit(s) type default name description 63:0 rwp 64'bx u0_dma a qword buffer for usb dma source/destination access. 8.8.2 usb source/destination dma data register 1 (u1_dma: 0x00330008) u1_dma is the usb source/destination dma data register (used by dma transmit channel #11 hardware for usb endpoint 1 in channel). not used by firmware. bit(s) type default name description 63:0 rwp 64'bx u1_dma a qword buffer for usb dma source/destination access. 8.8.3 usb source/destination dma data register 2 (u2_dma: 0x00330010) u2_dma is the usb source/destination dma data register (used by dma transmit channel #10 hardware for usb endpoint 2 in channel). not used by firmware. bit(s) type default name description 63:0 rwp 64'bx u2_dma a qword buffer for usb dma source/destination access. 8.8.4 usb source/destination dma data register 3 (u3_dma: 0x00330018) u3_dma is the usb source/destination dma data register (used by dma transmit channel #9 hardware for usb endpoint 3 in channel). not used by firmware. bit(s) type default name description 63:0 rwp 64'bx u3_dma a qword buffer for usb dma source/destination access.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 8-17 8.8.5 usb destination dma data register (ut_dma: 0x00330020) ut_dma is the usb destination dma data register (used by the usb dma receive hardware channel #12). not used by firmware. bit(s) type default name description 63:0 ro 64'bx ut_dma a qword buffer for usb dma destination access. 8.8.6 usb configuration data register (u_cfg: 0x00330024) u_cfg is the usb configuration data register. bit(s) type default name description 31:0 rw 32?b0 u_cfg udc configuration data transfer. requires successive 4-byte writes with handshaking control until all the configuration data has been transferred and the cfgdnint status bit is set. 8.8.7 usb interrupt data register (u_idat: 0x00330028) u_idat is the interrupt data register. bit(s) type default name description 31:0 rw 32?b0 u_idat usb interrupt channel data transfer. requires two successive writes with handshaking control for each 8-byte interrupt data packet.
cx82100 home network processor data sheet 8-18 conexant proprietary and confidential information 101306c 8.8.8 usb control register 1 (u_ctr1: 0x0033002c) bit(s) type default name description 31 rw 1'b0 usb_ie global usb interrupt enable. 0 = disable all usb related interrupts. 1 = enable all usb related interrupts enabled. each individual interrupt can be further controlled by its corresponding interrupt enable bit. 30 rw 1'b1 usb_reset usb reset. writing a 1 will reset the entire usb device (including the udc core) to default state. software must clear this bit by writing a 0 or reading it. this bit self-clears after being read. 29 rw 1'b0 ai_resume application initiated resume. this is an application initiated resume signal. writing a 1 to this bit will resume the usb bus from the suspended mode. the peripheral must assert the dev_resume signal to the udc core for one 12 mhz clock period. setting this bit is meaningful only when the usb bus is in the suspended mode. in response to this signal, the udc will deassert the udc_suspend signal, drive the non-idle (k state) onto the usb cable for 12 ms, and perform the remote wakeup operation. when the udc_suspend signal is deasserted in response to the assertion of the dev_resume signal, the peripheral must restart the clock (to the udc core) as soon as possible in order for the core to start the counters for counting the wakeup sequence time. this bit self-clears one cycle after it is been set. 28 rw 1?b0 rv_init buffer pointer initialized flag. set by firmware before activating out endpoints, but after writing the pointer to the circular rx dma buffer. must be reset by firmware at the next instruction. 27:16 rw 13'b0 reserved. should be written to all 0s. 15 rw 1'b0 ep3_in_dma_reset endpoint 3 in dma channel reset. writing a 1 to this bit resets the dma channel associated with the ep3_in endpoint. must be reset to a 0 by firmware and can be done immediately after setting to a 1. 14 rw 1'b0 ep2_in_dma_reset endpoint 2 in dma channel reset. writing a 1 to this bit resets the dma channel associated with the ep2_in endpoint. must be reset to a 0 by firmware and can be done immediately after setting to a 1. 13 rw 1'b0 ep1_in_dma_reset endpoint 1 in dma channel reset. writing a 1 to this bit resets the dma channel associated with the ep1_in endpoint. must be reset to a 0 by firmware and can be done immediately after setting to a 1.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 8-19 bit(s) type default name description 12 rw 1'b0 ep0_in_dma_reset endpoint 0 in dma channel reset. writing a 1 to this bit resets the dma channel associated with the ep0_in endpoint. must be reset to a 0 by firmware and can be done immediately after setting to a 1. 11 rw 1?b0 xver_sleep usb transceiver sleep mode select. 0 = do not power down the usb transceiver active. 1 = power down the usb transceiver. 10 rw 1?b0 intr_en interrupt endpoint enable. 0 = disable interrupt endpoint. 1 = enable interrupt endpoint. 9 rw 1?b0 ep3i_en endpoint 3 in enable. 0 = disable endpoint 3 in. 1 = enable endpoint 3 in. 8 rw 1?b0 ep2i_en endpoint 2 in enable. 0 = disable endpoint 2 in. 1 = enable endpoint 2 in. 7 rw 1?b0 ep1i_en endpoint 1 in enable. 0 = disable endpoint 1 in. 1 = enable endpoint 1 in. 6 rw 1?b0 ep0i_en endpoint 0 in enable. 0 = disable endpoint 0 in. 1 = enable endpoint 0 in. 5 rw 1?b0 ep3o_en endpoint 3 out enable. 0 = disable endpoint 3 out. 1 = enable endpoint 3 out. 4 rw 1?b0 ep2o_en endpoint 2 out enable. 0 = disable endpoint 2 out. 1 = enable endpoint 2 out. 3 rw 1?b0 ep1o_en endpoint 1 out enable. 0 = disable endpoint 1 out. 1 = enable endpoint 1 out. 2 rw 1?b0 ep0o_en endpoint 0 out enable. 0 = disable endpoint 0 out. 1 = enable endpoint 0 out. 1rw 1?b0 cfg_en udc configuration mode enable. 0 = disable udc configuration mode. 1 = enable udc configuration mode. 0 rw 1?b0 usb_en usb enable. 0 = disable usb. 1 = enable usb. never disable once enabled or the endpoints will not work!
cx82100 home network processor data sheet 8-20 conexant proprietary and confidential information 101306c 8.8.9 usb control register 2 (u_ctr2: 0x00330030) bit(s) type default name description 27:24 rw 4?b0 intr_addr endpoint 4 in address. 23:20 rw 4?b0 ep3i_addr endpoint 3 in address. 19:16 rw 4?b0 ep2i_addr endpoint 2 in address. 15:12 rw 4?b0 ep1i_addr endpoint 1 in address. 11:8 rw 4?b0 ep3o_addr endpoint 3 out address. 7:4 rw 4?b0 ep2o_addr endpoint 2 out address. 3:0 rw 4?b0 ep1o_addr endpoint 1 out address.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 8-21 8.8.10 usb control register 3 (u_ctr3: 0x00330034) bit(s) type default name description 29 rw 1?b0 ep3o_stall_en endpoint 3 out stall control. reset by the hardware when endpoint 3 out has been stalled. 28 rw 1?b0 ep2o_stall_en endpoint 2 out stall control. reset by the hardware when the endpoint has been stalled. 27 rw 1?b0 ep1o_stall_en endpoint 1 out stall control. reset by the hardware when the endpoint has been stalled. 26 rw 1?b0 ep0o_stall_en endpoint 0 out stall control. reset by the hardware when the endpoint has been stalled. 25 rw 1?b0 ep3i_stall_en endpoint 3 in stall control. reset by the hardware when the endpoint has been stalled. 24 rw 1?b0 ep2i_stall_en endpoint 2 in stall control. reset by the hardware when the endpoint has been stalled. 23 rw 1?b0 ep1i_stall_en endpoint 1 in stall control. reset by the hardware when the endpoint has been stalled. 22 rw 1?b0 ep0i_stall_en endpoint 0 in stall control. reset by the hardware when the endpoint has been stalled. 21 rw 1?b0 intr_stall_en interrupt endpoint stall control. reset by the hardware when the endpoint has been stalled. 20 rw 1?b0 rst_intr_errcnt reset for interrupt endpoint retries count. (nak count register) 19 rw 1?b0 rst_ep3i_errcnt reset for endpoint 3 in retries count. (nak count register) 18 rw 1?b0 rst_ep2i_errcnt reset for endpoint 2 in retries count. (nak count register) 17 rw 1?b0 rst_ep1i_errcnt reset for endpoint 1 in retries count. (nak count register) 16 rw 1?b0 rst_ep0i_errcnt reset for endpoint 0 in retries count. (nak count register) 15 1?b0 reserved. 14:12 rw 3?b0 intr_errcnt interrupt endpoint retries count. 11:9 rw 3?b0 ep3i_errcnt endpoint 3 in retries count. (nak count) 8:6 rw 3?b0 ep2i_errcnt endpoint 2 in retries count. (nak count) 5:3 rw 3?b0 ep1i_errcnt endpoint 1 in retries count. (nak count) 2:0 rw 3?b0 ep0i_errcnt endpoint 0 in retries count. (nak count)
cx82100 home network processor data sheet 8-22 conexant proprietary and confidential information 101306c 8.8.11 usb status (u_stat: 0x00330038) if an interrupt status bit in this register is set by the udc, the usb interrupt bit in the interrupt status register (int_stat) is set if the corresponding enable bit in the u_ier register is set. writing a 1 to a bit location will clear the interrupt status bit; writing a 0 has no effect. bit(s) type default name description 28 rr 1'b0 rx_pend_nonzero_int receive pending register nonzero interrupt. 0 = receive pending register is zero. 1 = receive pending register is nonzero. 27 rr 1'b0 udc_latchintfval_int udc_latchintfval interrupt. 0 = udc_latchintfval signal is not asserted. 1 = udc_latchintfval signal is asserted. the udc_latchintfval signal is asserted by the udc core for one clock, when the core receives a valid set-interface setup command to a supported interface and supported alternate interface setting. the signal is asserted when the udc issues an ack handshake to the setup transfer of the set-interface command. the interface to which this command is addressed is available on the udc_interfaceval[1:0] and the value of the new alternate setting is available on the udc_altintfval[2:0] outputs. using the udc_latchintfval signal, the application can know the set-interface command along with the interface number to which it is addressed to and the alternate setting value, without doing a full decode of the setup transfer. applications supporting dynamic alternate interfaces, can use this signal to identify the new alternate setting of the interface being selected. 26 rr 1'b0 udc_latchcfgval_int udc_latchcfgval interrupt. 0 = udc_latchcfgval signal is not asserted. 1 = udc_latchcfgval signal is asserted. the udc_latchcfgval signal is asserted by the udc core for one clock, when the core receives a valid set-configuration setup command to a supported configuration. the signal is asserted when the udc issues an ack handshake to the setup transfer of the set-configuration command. the value of the new configuration is available on the udc_configval[1:0] outputs. using the udc_latchcfgval signal, the application can know the set-configuration command and the configuration value with out doing a full decode of the setup transfer. applications supporting dynamic configurations or applications that do power management based on the current configuration, can use this signal to identify the new configuration the device is being selected.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 8-23 bit(s) type default name description 25 rr 1'b0 udc_usbreset_int udc_usbreset interrupt. 0 = udc_usbreset signal is not asserted. 1 = udc_usbreset signal is asserted. the udc_usbreset signal is asserted by the udc core whenever the core observes more than 2.5 us (32 fs bit times/4 ls bit times) of se0 on the d+/d- lines. once asserted, udc_usbreset is kept asserted as long as the se0 is observed on the d+/d- lines. 24 rr 1'b0 udc_sof_int udc_sof interrupt. 0 = udc_sof signal is not asserted. 1 = udc_sof signal is asserted. the udc_sof signal is asserted by the udc core for one clock every time an entire sof packet is successfully decoded on the usb. the udc_sof signal is at logic ?0? when reset and when asserted will be at logic ?1?. 23 rr 1'b0 usb_suspend_int usb suspend detected interrupt. 0 = usb cable not in suspend mode. 1 = usb cable in suspend mode. udc has detected that the usb cable is in the suspended mode i.e., the usb is idle for 3 ms. the device should go into suspend mode whenever this bit is on and should meet all the usb specification requirements for the suspend mode. it is the responsibility of the peripheral to stop the clock so that min. power is consumed when the device is in suspended mode. 22 rr 1?b0 usb_resume_int usb resume detected interrupt. 0 = usb cable not in resume mode. 1 = usb cable in resume mode. udc has detected a non- idle (k state) on the usb cable while the usb cable is in suspended mode. 21 rr 1?b0 ep3i_invldhdr_int endpoint 3 in invalid header interrupt. 0 = invalid header not detected. 1 = invalid header detected for endpoint 3 in channel buffer list. 20 rr 1?b0 ep2i_invldhdr_int endpoint 2 in invalid header interrupt. 0 = invalid header not detected. 1 = invalid header detected for endpoint 2 in channel buffer list. 19 rr 1?b0 ep1i_invldhdr_int endpoint 1 in invalid header interrupt. 0 = invalid header not detected. 1 = invalid header detected for endpoint 1 in channel buffer list. 18 rr 1?b0 ep0i_invldhdr_int endpoint 0 in invalid header interrupt. 0 = invalid header not detected. 1 = invalid header detected for endpoint 0 in channel buffer list. 17 rr 1?b0 intr_nak_int interrupt channel naked on current transfer. 16 rr 1?b0 intr_errcnt_int interrupt channel exceeded max retries count.
cx82100 home network processor data sheet 8-24 conexant proprietary and confidential information 101306c bit(s) type default name description 15 rr 1?b0 ep3i_errcnt_int endpoint 3 in error count interrupt. 0 = endpoint 3 in retries count not exceeded. 1 = endpoint 3 in retries count exceeded. 14 rr 1?b0 ep2i_errcnt_int endpoint 2 in error count interrupt. 0 = endpoint 2 in retries count not exceeded. 1 = endpoint 2 in retries count exceeded. 13 rr 1?b0 ep1i_errcnt_int endpoint 1 in error count interrupt. 0 = endpoint 1 in retries count not exceeded. 1 = endpoint 1 in retries count exceeded. 12 rr 1?b0 ep0i_errcnt_int endpoint 0 in error count interrupt. 0 = endpoint 0 in retries count not exceeded. 1 = endpoint 0 in retries count exceeded. 11 rr 1?b0 intrnext_int interrupt channel requesting next interrupt. 0 = interrupt channel not requesting second dword write of interrupt data. 1 = interrupt channel requesting second dword write of interrupt data. 10 rr 1?b0 intrdn_int interrupt channel transmission done interrupt. 0 = interrupt channel transmission is not complete. 1 = interrupt channel transmission is complete. 9 rr 1?b0 ep3i_int endpoint 3 in transmission complete interrupt. 0 = endpoint 3 in channel transmission is not complete. 1 = endpoint 3 in channel transmission is complete. 8 rr 1?b0 ep2i_int endpoint 2 in transmission complete interrupt. 0 = endpoint 2 in channel transmission is not complete. 1 = endpoint 2 in channel transmission is complete. 7 rr 1?b0 ep1i_int endpoint 1 in transmission complete interrupt. 0 = endpoint 1 in channel transmission is not complete. 1 = endpoint 1 in channel transmission is complete. 6 rr 1?b0 ep0i_int endpoint 0 in transmission complete interrupt. 0 = endpoint 0 in channel transmission is not complete. 1 = endpoint 0 in channel transmission is complete. 5rr 1?b0ep3o_int endpoint 3 out reception complete interrupt. 0 = endpoint 3 out channel reception is not complete. 1 = endpoint 3 out channel reception is complete. 4rr 1?b0ep2o_int endpoint 2 out reception complete interrupt. 0 = endpoint 2 out channel reception is not complete. 1 = endpoint 2 out channel reception is complete. 3rr 1?b0ep1o_int endpoint 1 out reception complete interrupt. 0 = endpoint 1 out channel reception is not complete. 1 = endpoint 1 out channel reception is complete. 2rr 1?b0ep0o_int endpoint 0 out reception complete interrupt. 0 = endpoint 0 out channel reception is not complete. 1 = endpoint 0 out channel reception is complete. 1rr 1?b0cfgdn_int udc configuration done interrupt. 0 = udc configuration is not complete. 1 = udc configuration is complete. 0rr 1?b0cfgnext_int next configuration data dword requested interrupt. 0 = next configuration data dword is not requested. 1 = next configuration data dword is requested.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 8-25 8.8.12 usb interrupt enable register (u_ier: 0x0033003c) writing a 1 to a bit location will enable setting of the usb interrupt bit in the interrupt status register (int_stat) if the corresponding interrupt status bit is set in the usb_stat register. writing a 0 to a bit location will disable setting the usb interrupt bit in the int_stat register due to the corresponding interrupt status bit. bit(s) type default name description 28 rw 1'b0 rx_pend_nonzero_inten rx_pend_nonzero_int interrupt enable. 27 rw 1'b0 udc_latchintfval_inten udc_latchintfval_int interrupt enable. 26 rw 1?b0 udc_latchcfgval_inten udc_latchcfgval_int interrupt enable. 25 rw 1?b0 udc_usbreset_inten udc_usbreset_int interrupt enable. 24 rw 1?b0 udc_sof_inten udc_sof_int interrupt enable. 23 rw 1'b0 usb_suspend_inten usb_suspend_int interrupt enable. 22 rw 1?b0 usb_resume_inten usb_resume_int interrupt enable. 21 rw 1?b0 ep3i_invldhdr_inten ep3i_invldhdr_int interrupt enable. 20 rw 1?b0 ep2i_invldhdr_inten ep2i_invldhdr_int interrupt enable. 19 rw 1?b0 ep1i_invldhdr_inten ep1i_invldhdr_int interrupt enable. 18 rw 1?b0 ep0i_invldhdr_inten ep0i_invldhdr_int interrupt enable. 17 rw 1?b0 intr_nak_inten intr_nak_int interrupt enable. 16 rw 1?b0 intr_errcnt_inten intr_errcnt_int interrupt enable. 15 rw 1?b0 ep3i_errcnt_inten ep3i_errcnt_int interrupt enable. 14 rw 1?b0 ep2i_errcnt_inten ep2i_errcnt_int interrupt enable. 13 rw 1?b0 ep1i_errcnt_inten ep1i_errcnt_int interrupt enable. 12 rw 1?b0 ep0i_errcnt_inten ep0i_errcnt_int interrupt enable. 11 rw 1?b0 intrnext_inten intrnext_int interrupt enable. 10 rw 1?b0 intrdn_inten intrdn_int interrupt enable. 9 rw 1?b0 ep3i_inten ep3i_int interrupt enable. 8 rw 1?b0 ep2i_inten ep2i_int interrupt enable. 7 rw 1?b0 ep1i_inten ep1i_int interrupt enable. 6 rw 1?b0 ep0i_inten ep0i_int interrupt enable. 5 rw 1?b0 ep3o_inten ep3o_int interrupt enable. 4 rw 1?b0 ep2o_inten ep2o_int interrupt enable. 3 rw 1?b0 ep1o_inten ep1o_int interrupt enable. 2 rw 1?b0 ep0o_inten ep0o_int interrupt enable. 1 rw 1?b0 cfgdn_inten cfgdn_int interrupt enable. 0 rw 1?b0 cfgnext_inten cfgnext_int interrupt enable.
cx82100 home network processor data sheet 8-26 conexant proprietary and confidential information 101306c 8.8.13 usb status register 2 (u_stat2: 0x00330040) if an interrupt status bit in this register is set by the udc, the usb interrupt bit in the interrupt status register (int_stat) is set if the corresponding enable bit in the u_ier2 register is set. writing a 1 to a bit location will clear the interrupt status bit; writing a 0 has no effect. bit(s) type default name description 31 rr 1?b0 ep3in_pendtozero_int endpoint 3 pending register equals 0. 1 = the endpoint 3 pending register (ep3_in_tx _pend) has transitioned to zero. 30 rr 1?b0 ep2in_pendtozero_int endpoint 2 pending register equals 0. 1 = the endpoint 2 pending register (ep2_in_tx _pend) has transitioned to zero. 29 rr 1?b0 ep1in_pendtozero_int endpoint 1 pending register equals 0. 1 = the endpoint 1 pending register (ep1_in_tx _pend) has transitioned to zero. 28 rr 1?b0 ep0in_pendtozero_int endpoint 0 pending register equals 0. 1 = the endpoint 0 pending register (ep0_in_tx _pend) has transitioned to zero. 26 rr 1'b0 ep_out_watch_int receive dma watchdog timer expired interrupt. 1 = all of the following conditions have occurred: ? the watchdog timer is enabled by having a nonzero value in register usb_rxtimer. ? the receive dma watchdog timer register counter (usb_rxtimercnt) has expired (gone to zero). ? the received pending register (ep_out_rx_pend) value is nonzero. 25 rr 1?b0 ep_out_pendlevel_int receive usb pending level interrupt. 1 = the host receive buffer has received the number of packets specified in the receive pending interrupt level register (ep_out_pendlevel). note: the interrupt is automatically cleared when the ep_out_rx_clrpend bit in u_csr register is written with a one. 24 rr 1'b0 rx_overrun_int receive overrun interrupt. note: "receiver overrun" occurs when the rx dma receiver continues to receive new packet while the receive packet pending register (ep_out_rx_pend) value equals the maximum packet size (ep_out_rx_bufsize). it is possible that the software will write a new value to the receive decrement register before handling the overrun interrupt. if this happens, the h/w will proceed to update rx_pend as normal, but won't issue any dma transfers as long as the overrun interrupt flag is still pending. 23 rr 1'b0 cfgset_cmd_int set configuration command detected interrupt. 22 rr 1'b0 intfset_cmd_int set interface command detected interrupt. 21 rr 1'b0 cur_cfg_int current configuration detected interrupt. 20 rr 1'b0 cur_intf_int current interface detected interrupt. 19 rr 1'b0 altset_cmd_int alt set command detected interrupt. 18 rr 1'b0 setup_cmd_int setup command detected interrupt. 17 rr 1'b0 ep3o_stall_clr_int ep3_out stall clear interrupt.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 8-27 bit(s) type default name description 16 rr 1'b0 ep2o_stall_clr_int ep2_out stall clear interrupt. 15 rr 1'b0 ep1o_stall_clr_int ep1_out stall clear interrupt. 14 rr 1'b0 ep0o_stall_clr_int ep0_out stall clear interrupt. 13 rr 1'b0 ep3i_stall_clr_int ep3_in stall clear interrupt. 12 rr 1'b0 ep2i_stall_clr_int ep2_in stall clear interrupt. 11 rr 1'b0 ep1i_stall_clr_int ep1_in stall clear interrupt. 10 rr 1'b0 ep0i_stall_clr_int ep0_in stall clear interrupt. 9 rr 1'b0 intr_stall_clr_int interrupt channel stall clear interrupt. 8 rr 1'b0 ep3o_stall_int ep3_out stall interrupt. 7 rr 1'b0 ep2o_stall_int ep2_out stall interrupt. 6 rr 1'b0 ep1o_stall_int ep1_out stall interrupt. 5 rr 1'b0 ep0o_stall_int ep0_out stall interrupt. 4 rr 1'b0 ep3i_stall_int ep3_in stall interrupt. 3 rr 1'b0 ep2i_stall_int ep2_in stall interrupt. 2 rr 1'b0 ep1i_stall_int ep1_in stall interrupt. 1 rr 1'b0 ep0i_stall_int ep0_in stall interrupt. 0 rr 1'b0 intr_stall_int interrupt channel stall interrupt.
cx82100 home network processor data sheet 8-28 conexant proprietary and confidential information 101306c 8.8.14 usb interrupt enable register 2 (u_ier2: 0x00330044) writing a 1 to a bit location will enable setting of the usb interrupt in the interrupt status register (int_stat) if the corresponding interrupt status bit is set in the usb_stat2 register. writing a 0 will disable setting the usb interrupt bit in the int_stat register due to the corresponding interrupt status bit. bit(s) type default name description 31 rw 1?b0 ep3in_pendtozero_inten ep3in_pendtozero_int interrupt enable. 30 rw 1?b0 ep2in_pendtozero_inten ep2in_pendtozero_int interrupt enable. 29 rw 1?b0 ep1in_pendtozero_inten ep1in_pendtozero_int interrupt enable. 28 rw 1?b0 ep0in_pendtozero_inten ep0in_pendtozero_int interrupt enable. 26 rw 1'b0 ep_out_watch_inten ep_out_watch_int interrupt enable. 25 rw 1?b0 ep_out_pendlevel_inten ep_out_pendlevel_int interrupt enable. 24 rr 1'b0 rx_overrun_inten rx_overrun_int interrupt enable. 23 rr 1'b0 cfgset_cmd_inten cfgset_cmd_int interrupt enable. 22 rr 1'b0 intfset_cmd_inten intfset_cmd_int interrupt enable. 21 rr 1'b0 cur_cfg_inten cur_cfg_int interrupt enable. 20 rr 1'b0 cur_intf_inten cur_intf_int interrupt enable. 19 rr 1'b0 altset_cmd_inten altset_cmd_int interrupt enable. 18 rr 1'b0 setup_cmd_inten setup_cmd_int interrupt enable. 17 rr 1'b0 ep3o_stall_clr_inten ep3o_stall_clr_int interrupt enable. 16 rr 1'b0 ep2o_stall_clr_inten ep2o_stall_clr_int interrupt enable. 15 rr 1'b0 ep1o_stall_clr_inten ep1o_stall_clr_int interrupt enable. 14 rr 1'b0 ep0o_stall_clr_inten ep0o_stall_clr_int interrupt enable. 13 rr 1'b0 ep3i_stall_clr_inten ep3i_stall_clr_int interrupt enable. 12 rr 1'b0 ep2i_stall_clr_inten ep2i_stall_clr_int interrupt enable. 11 rr 1'b0 ep1i_stall_clr_inten ep1i_stall_clr_int interrupt enable. 10 rr 1'b0 ep0i_stall_clr_inten ep0i_stall_clr_int interrupt enable. 9 rr 1'b0 intr_stall_clr_inten intr_stall_clr_int interrupt enable. 8 rr 1'b0 ep3o_stall_inten ep3o_stall_int interrupt enable. 7 rr 1'b0 ep2o_stall_inten ep2o_stall_int interrupt enable. 6 rr 1'b0 ep1o_stall_inten ep1o_stall_int interrupt enable. 5 rr 1'b0 ep0o_stall_inten ep0o_stall_int interrupt enable. 4 rr 1'b0 ep3i_stall_inten ep3i_stall_int interrupt enable. 3 rr 1'b0 ep2i_stall_inten ep2i_stall_int interrupt enable. 2 rr 1'b0 ep1i_stall_inten ep1i_stall_int interrupt enable. 1 rr 1'b0 ep0i_stall_inten ep0i_stall_int interrupt enable. 0 rr 1'b0 intr_stall_inten intr_stall_int interrupt enable.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 8-29 8.8.15 udc time stamp register (udc_tsr: 0x0033008c) bit(s) type default name description 10:0 ro 11'b0 udc_timestamp (latched version of the udc_timestamp [10:0] when udc_sof is asserted by the udc core.) the timestamp information obtained in the sof packet. the value on this bus is valid when the udc_sof signal is asserted high. 8.8.16 udc status register (udc_stat: 0x00330090) note: used for debugging purpose only. bit(s) type default name description 11:9 ro 3'b0 udc_altintfval (latched version of the udc_altintfval [2:0] when udc_latchintfval is asserted by the udc core.) udc_altintfval[1:0] contains the new alternate interface value selected in the specified interface in the set-interface command. the value on this three bit bus is valid when the udc_latchintfval signal is asserted. the udc supports a maximum of eight alternate settings per interface. 8:7 ro 2'b0 udc_interfaceval (latched version of the udc_interfaceval [1:0] when udc_latchintfval is asserted by the udc core.) udc_interfaceval[1:0] contains the interface number to which the set-interface command is issued to change the alternate setting of the interface. the value on this two bits bus is valid when the udc_latchintfval signal is asserted. the udc supports a maximum of four interfaces and eight alternates in each interface. 6:5 ro 2'b0 udc_configval (latched version of the udc_configval [1:0] when udc_latchcfgval is asserted by the udc core.) udc_configval[1:0] contains the new configuration value that is being issued by the host in the set-configuration command. the value on this two bits bus is valid when the udc_latchcfgval signal is asserted. the udc supports a maximum of three configurations plus one unconfigured state (cfg-00). 4 ro 1'b0 txenl (buffered version of the txenl signal from the udc core.) output enable for the differential driver to transmit the data onto the usb. when the udc is in transmit mode, this signal is asserted which enables the output drivers. this signal at reset time is a 1 and when asserted goes to a 0. 3 ro 1'b0 txdmns (buffered version of the txdmns signal from the udc core.) nrzi formatted d- output data to the usb. when the udc is in the transmit mode, the d- data to be sent out is transmitted via this signal. this signal will be fed into the differential driver. 2 ro 1'b0 txdpls (buffered version of the txdpls signal from the udc core.) nrzi formatted d+ output data to the usb. when the udc is in transmit mode, the d+ data to be sent out is transmitted via this signal. this signal will be fed into the differential driver. 1 ro 1'b0 dmns (buffered version of the dmns signal to the udc core.) d- signal from the usb to identify the se0 signal. 0 ro 1'b0 dpls (buffered version of the dpls signal to the udc core.) d+ signal from the usb to identify the se0 signal.
cx82100 home network processor data sheet 8-30 conexant proprietary and confidential information 101306c 8.9 usb dma control registers 8.9.1 ep0_in transmit increment register (ep0_in_tx_inc: 0x00330048) bit(s) type default name description 7:0 rw 8'b0 ep0_in_tx _inc transmit increment register for ep0_in. no. of new valid packets in the ep0_in host buffer ready to be transferred by the dmac. updated by firmware. 8.9.2 ep0_in transmit pending register (ep0_in_tx_pend: 0x0033004c) bit(s) type default name description 7:0 ro 8'b0 ep0_in_tx _pend transmit pending register for ep0_in. no. of existing pending packets in the ep0_in host buffer ready to be transferred by host. 8.9.3 ep0_in transmit qword count register (ep0_in_tx_qwcnt: 0x00330050) bit(s) type default name description 3:0 ro 4'b0 ep0_in_tx _qwcnt transmit qword count register for ep0_in. used by hardware. 8.9.4 ep1_in transmit increment register (ep1_in_tx_inc: 0x00330054) bit(s) type default name description 7:0 rw 8'b0 ep1_in_tx _inc transmit increment register for ep1_in. no. of new valid packets in the ep1_in host buffer ready to be transferred by the dmac. updated by firmware.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 8-31 8.9.5 ep1_in transmit pending register (ep1_in_tx_pend: 0x00330058) bit(s) type default name description 7:0 ro 8'b0 ep1_in_tx _pend transmit pending register for ep1_in. no. of existing pending packets in the ep1_in host buffer ready to be transferred by host. 8.9.6 ep1_in transmit qword count register (ep1_in_tx_qwcnt) bit(s) type default name description 3:0 ro 4'b0 ep1_in_tx _qwcnt transmit qword count register for ep1_in. used by hardware. 8.9.7 ep2_in transmit increment register (ep2_in_tx_inc: 0x00330060) bit(s) type default name description 7:0 rw 8'b0 ep2_in_tx _inc transmit increment register for ep2_in. no. of new valid packets in the ep2_in host buffer ready to be transferred by the dmac. updated by firmware. 8.9.8 ep2_in transmit pending register (ep2_in_tx_pend: 0x00330064) bit(s) type default name description 7:0 ro 8'b0 ep2_in_tx _pend transmit pending register for ep2_in. no. of existing pending packets in the ep2_in host buffer ready to be transferred by host.
cx82100 home network processor data sheet 8-32 conexant proprietary and confidential information 101306c 8.9.9 ep2_in transmit qword count register (ep2_in_tx_qwcnt) bit(s) type default name description 3:0 ro 4'b0 ep2_in_tx _qwcnt transmit qword count register for ep2_in. used by hardware. 8.9.10 ep3_in transmit increment register (ep1_in_tx_inc: 0x0033006c) bit(s) type default name description 7:0 rw 8'b0 ep3_in_tx _inc transmit increment register for ep3_in. no. of new valid packets in the ep3_in host buffer ready to be transferred by the dmac. updated by firmware. 8.9.11 ep3_in transmit pending register (ep3_in_tx_pend: 0x00330070) bit(s) type default name description 7:0 ro 8'b0 ep3_in_tx _pend transmit pending register for ep3_in. no. of existing pending packets in the ep3_in host buffer ready to be transferred to host. 8.9.12 ep3_in transmit qword count register (ep3_in_tx_qwcnt: 0x00330074) bit(s) type default name description 3:0 ro 4'b0 ep3_in_tx _qwcnt transmit qword count register for ep3_in. used by hardware.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 8-33 8.9.13 ep_out receive decrement register (ep_out_rx_dec: 0x00330078) bit(s) type default name description 7:0 rw 8'b0 ep_out_rx _dec endpoint out receive decrement register. no. of packets that have been transferred from the host rx dma buffer. updated by firmware. 8.9.14 ep_out receive pending register (ep_out_rx_pend: 0x0033007c) bit(s) type default name description 7:0 ro 8'b0 ep_out_rx_pend endpoint out receive pending register. no. of received packets that have been transferred to the host rx dma buffer by the usb dma dmac channel. note: no new packets will be transferred if ep_out_pend = ep_bufsize. 8.9.15 ep_out receive buffer size register (ep_out_rx_bufsize: 0x00330084) bit(s) type default name description 7:0 rw 8'b0 ep_out_rx_bufsize total received packet size. should be less than or equal 226, should match with value programmed into dmac_12_cnt1 register minus one count. using the following formula given the usb rx dma size (dma_size) in bytes, dma_size < = 16376 and a multiple integer number of 72 dmac_12_cnt1 = (dma_size / 8) count value = ((dma_size) / 72) -1 8.9.16 ep_out receive qword count register (ep_out_rx_qwcnt: 0x00330080) bit(s) type default name description 3:0 ro 4'b0 ep_out_rx_qwcnt receive qword count register. used by hardware.
cx82100 home network processor data sheet 8-34 conexant proprietary and confidential information 101306c 8.9.17 usb receive dma watchdog timer register (usb_rxtimer: 0x00330094) bit(s) type default name description 15:0 rw 16'b0 usb_rxtimer usb receive dma watchdog timer register. 0 = disabled. 0 = value copied into the usb_rxtimercnt bits 23:8 whenever the receive pending register value (ep_out_rx_pend) changes (increments) to a nonzero value. see register usb_rxtimercnt for more information. 8.9.18 usb receive dma watchdog timer counter register (usb_rxtimercnt: 0x00330098) bit(s) type default name description 23:0 ro 24'b0 usb_rxtimercnt usb receive dma watchdog timer counter register. this counter will start running whenever a nonzero value is contained in usb_rxtimer register and the receive pending register (ep_out_rx_pend) value becomes nonzero. the counter therefore automatically reloads the usb_rxtimer value when it counts down to zero (this reload condition doesn?t matter since timer has stopped) or after a reception of a usb packet. if bit 25 of u_ier2 is set to a 1, an interrupt will be generated when the counter reaches zero. this is reflected in bit 25 of u_stat2. ?start running? means that the 16 bits of the usb_rxtimer register are copied to bits 24:8 of the counter. this allows a timer range between 256 cycles pclk (5.12 us if pclk = 50mhz) and 16m cycles pclk (~335.5ms if pclk = 50mhz). the counter will stop running when the usb_rxtimer register is programmed to 0 or the ep_out_rx_pend is 0. 8.9.19 ep_out receive pending interrupt level register (ep_out_rx_pendlevel: 0x0033009c) table 8-10. ep_out receive pending level register bit(s) type default name description 7:0 rw 8'b0 ep_out_rx_pendlevel receive packet pending interrupt level. when the value in the receive pending register (ep_out_rx_pend) equals the value in this register, an interrupt will be generated if enabled.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 8-35 8.9.20 usb control-status register (u_csr: 0x00330088) bit(s) type default name self clears 14 ro 1'b0 ep_out_rx_pendisfull receive pending register for all out endpoints full status. 0 = receive pending register for all the out endpoints is not full. 1 = receive pending register for all the out endpoints is full. 13 ro 1'b1 ep3_in_tx_pendiszero transmit pending register for ep3_in zero status. 0 = transmit pending register for ep3_in is nonzero. 1 = transmit pending register for ep3_in is zero. 12 ro 1'b1 ep2_in_tx_pendiszero transmit pending register for ep2_in zero status. 0 = transmit pending register for ep2_in is nonzero. 1 = transmit pending register for ep2_in is zero. 11 ro 1'b1 ep1_in_tx_pendiszero transmit pending register for ep1_in zero status. 0 = transmit pending register for ep1_in is nonzero. 1 = transmit pending register for ep1_in is zero. 10 ro 1'b1 ep0_in_tx_pendiszero transmit pending register for ep0_in is zero status. 0 = transmit pending register for ep0_in is nonzero. 1 = transmit pending register for ep0_in is zero. 9 wo 1'b0 ep_out_rx_clrqwcnt clear receive qwcnt register for all out endpoints. 0 = no effect. 1 = clear the receive qwcnt register for all out endpoints. this bit self-clears one cycle after a 1 is written. 8 wo 1?b0 ep_out_rx_clrpend clear receive pending register for all out endpoints. 0 = no effect. 1 = clear the receive pending register for all out endpoints. this bit self-clears one cycle after a 1 is written. 7 wo 1?b0 ep3_in_tx_clrqwcnt clear the transmit qwcnt register for ep3_in. 0 = no effect. 1 = clear the transmit qwcnt register for ep3_in. this bit self-clears one cycle after a 1 is written. 6 wo 1'b0 ep3_in_tx_clrpend clear the transmit pending register for ep3_in. 0 = no effect. 1 = clear the transmit pending register for ep3_in. this bit self-clears one cycle after a 1 is written. 5 wo 1'b0 ep2_in_tx_clrqwcnt clear the transmit qwcnt register for ep2_in. 0 = no effect. 1 = clear the transmit qwcnt register for ep2_in. this bit self-clears one cycle after a 1 is written. 4 wo 1'b0 ep2_in_tx_clrpend clear the transmit pending register for ep2_in. 0 = no effect. 1 = clear the transmit pending register for ep2_in. this bit self-clears one cycle after a 1 is written. 3 wo 1'b0 ep1_in_tx_clrqwcnt clear the transmit qwcnt register for ep1_in. 0 = no effect. 1 = clear the transmit qwcnt register for ep1_in. this bit self-clears one cycle after a 1 is written.
cx82100 home network processor data sheet 8-36 conexant proprietary and confidential information 101306c bit(s) type default name self clears 2 wo 1'b0 ep1_in_tx_clrpend clear the transmit pending register for ep1_in. 0 = no effect. 1 = clear the transmit pending register for ep1_in. this bit self-clears one cycle after a 1 is written. 1 wo 1'b0 ep0_in_tx_clrqwcnt clear the transmit qwcnt register for ep0_in. 0 = no effect. 1 = clear the transmit qwcnt register for ep0_in. this bit self-clears one cycle after a 1 is written. 0 wo 1'b0 ep0_in_tx_clrpend clear the transmit qwcnt register for ep0_in. 0 = no effect. 1 = clear the transmit qwcnt register for ep0_in. this bit self-clears one cycle after a 1 is written.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 9-1 9 general purpose input/output interface description 9.1 gpio pin description the gpio pins can be read by reading gpio_data_in{x} register. they can be driven as outputs by using gpio_oe{x} for the pin driver enable, and gpio_data_out{x} for the data output polarity. each gpio[x] pin is controlled individually by gpio_oe{x} for the input/output direction. all gpio pins can serve as external interrupt inputs. these are controlled through gpio_isr{x} and gpio_ier{x} registers. the polarity and the sensitivity (i.e., edge or level) for each gpio interrupt source can be controlled by programming the gpio_ipc{x} and gpio_ism{x} registers, respectively. gpio[39:37; 32] have alternate functions that can be controlled through the gpio option register (gpio_opt). figure 9-1 illustrates the internal interface for a gpio pin. figure 9-1. gpio[x] interface 100545_061 gpio[x] gpio_oe{x} gpio_data_out{x} local data bus 1 0 gpio_data_in{x}
cx82100 home network processor data sheet 9-2 conexant proprietary and confidential information 101306c 9.2 gpio register memory map gpio registers are identified in table 9-1. table 9-1. gpio registers register label register name asb address type default value ref. gpio_ism1 gpio interrupt sensitivity mode register 1 0x003500a0 rw 0x00000000 9.3.20 gpio_ism2 gpio interrupt sensitivity mode register 2 0x003500a4 rw 0x00000000 9.3.21 gpio_ism3 gpio interrupt sensitivity mode register 3 0x003500a8 rw 0x00000000 9.3.22 gpio_opt gpio option register 0x003500b0 rw 0x00000000 9.3.1 gpio_oe1 gpio output enable register 1 0x003500b4 rw 0x00002306 9.3.2 gpio_oe2 gpio output enable register 2 0x003500b8 rw 0x00000082 9.3.3 gpio_oe3 gpio output enable register 3 0x003500bc rw 0x00000000 9.3.4 gpio_data_in1 gpio data input register 1 0x003500c0 ro 0x00000000 9.3.5 gpio_data_in2 gpio data input register 2 0x003500c4 ro 0x00000000 9.3.6 gpio_data_in3 gpio data input register 3 0x003500c8 ro 0x00000000 9.3.7 gpio_data_out1 gpio data output register 1 0x003500cc rw 0x23062306 9.3.8 gpio_data_out2 gpio data output register 2 0x003500d0 rw 0x00960086 9.3.9 gpio_data_out3 gpio data output register 3 0x003500d4 rw 0x00000000 9.3.10 gpio_isr1 gpio interrupt status register 1 0x003500d8 rr 0x00000000 9.3.11 gpio_isr2 gpio interrupt status register 2 0x003500dc rr 0x00000000 9.3.12 gpio_isr3 gpio interrupt status register 3 0x003500e0 rr 0x00000000 9.3.13 gpio_ier1 gpio interrupt enable register 1 0x003500e4 rw 0x00000000 9.3.14 gpio_ier2 gpio interrupt enable register 2 0x003500e8 rw 0x00000000 9.3.15 gpio_ier3 gpio interrupt enable register 3 0x003500ec rw 0x00000000 9.3.16 gpio_ipc1 gpio interrupt polarity control register 1 0x003500f0 rw 0x00000000 9.3.17 gpio_ipc2 gpio interrupt polarity control register 2 0x003500f4 rw 0x00000000 9.3.18 gpio_ipc3 gpio interrupt polarity control register 3 0x003500f8 rw 0x00000000 9.3.19
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 9-3 9.3 gpio registers gpio register bits are described in this section. 9.3.1 gpio option register for gpio[39:37; 32] (gpio_opt: 0x003500b0) this register selects general or special purpose use for the gpio[39:37; 32] pins. note: voltage levels for gpio[39:37; 32] pins assigned to special purpose functions by bits in the gpio_opt register are reflected in the gpio_data_in3 register, however, the gpio_data_out3 register bits are not applicable. bit(s) type default name description 31:8 reserved. 7 rw 1?b0 gpio_sel7 select fclkio or gpio39 usage. 0 = fclkio/gpio39 pin is used as gpio39. 1 = fclkio/gpio39 pin is used as fclkio. note: pin pllbp high causes fclkio to be selected regardless of this bit state. 6 rw 1?b0 gpio_sel6 select bclkio or gpio38 usage. 0 = bclkio/gpio38 pin is used as gpio38. 1 = bclkio/gpio38 pin is used as bclkio. note: pin pllbp high causes bclkio to be selected regardless of this bit state. 5 rw 1?b0 gpio_sel5 select gpio37 or hcs4# usage. 0 = had31 (hcs4#)/gpio37 pin is used as hcs4#. 1 = had31 (hcs4#)/gpio37 pin is used as a gpio37. 4:1 reserved. 0 rw 1?b0 gpio_sel0 select gpio32 or hcs0# usage. 0 = hc00 (hcs0#)/gpio32 pin is used as hcs0#. 1 = hc00 (hcs0#)/gpio32 pin is used as gpio32.
cx82100 home network processor data sheet 9-4 conexant proprietary and confidential information 101306c 9.3.2 gpio output enable register 1 for gpio[15:14; 8:5] (gpio_oe1: 0x003500b4) gpio_oe1 is the output enable register for gpio[15:14; 8:5]. bit(s) type default name description 15:0; 15 y 0, y = bit # rw 16?b0 gpio_oe{x}, 15 x 0, x = y gpio[x] output enable, 15 x 0. 0 = gpio[x] is an input pin. 1 = gpio[x] is an output pin. bit(s) type default name description 31:16 reserved. 15 rw 1?b0 gpio_oe15 gpio15 output enable. 14 rw 1?b0 gpio_oe14 gpio14 output enable. 13:9 reserved. 8rw1?b0gpio_oe8 gpio8 output enable. 7rw1?b0gpio_oe7 gpio7 output enable. 6rw1?b0gpio_oe6 gpio6 output enable. 5rw1?b0gpio_oe5 gpio5 output enable. 4:0 reserved. 9.3.3 gpio output enable register 2 for gpio[31; 27:16] (gpio_oe2: 0x003500b8) gpio_oe2 is the output enable register for gpio[31; 27:16] bit(s) type default name description 15:0; 15 y 0, y = bit # rw 16?b0 gpio_oe{x}, 31 x 16, x = y + 16 gpio[x] output enable, 31 x 16. 0 = gpio[x] is an input pin. 1 = gpio[x] is an output pin. bit(s) type default name description 31:16 reserved. 15 rw 1?b0 gpio_oe31 gpio31 output enable. 14:12 reserved. 11 rw 1?b0 gpio_oe27 gpio27 output enable. 10 rw 1?b0 gpio_oe26 gpio26 output enable. 9rw1?b0gpio_oe25 gpio25 output enable. 8rw1?b0gpio_oe24 gpio24 output enable. 7 reserved. 6rw1?b0gpio_oe22 gpio22 output enable. 5rw1?b0gpio_oe21 gpio21 output enable. 4rw1?b0gpio_oe20 gpio20 output enable. 3rw1?b0gpio_oe19 gpio19 output enable. 2rw1?b0gpio_oe18 gpio18 output enable. 1rw 1gpio_oe17 gpio17 output enable. 0rw1?b0gpio_oe16 gpio16 output enable.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 9-5 9.3.4 gpio output enable register 3 for gpio[39:37; 32] (gpio_oe3: 0x003500bc) gpio_oe3 is the output enable register for gpio[39:37; 32]. bit(s) type default name description 7:0; 7 y 0, y = bit # rw 8?b0 gpio_oe{x}, 39 x 32, x = y + 32 gpio[x] output enable, 39 x 32. 0 = gpio[x] is an input pin. 1 = gpio[x] is an output pin. bit(s) type default name description 31:8 reserved. 7rw1?b0gpio_oe39 gpio39 output enable. 6rw1?b0gpio_oe38 gpio38 output enable. 5rw1?b1gpio_oe37 gpio37 output enable. 4:1 reserved. 0rw1?b1gpio_oe32 gpio32 output enable. 9.3.5 gpio data input register 1 for gpio[15:14; 8:5] (gpio_data_in1: 0x003500c0) gpio_data_in1is the data input register for gpio[15:14; 8:5]. bit(s) type default name description 15:0; 15 y 0, y = bit # ro 16?bx gpio_din {x}, 15 x 0, x = y gpio[x] pin voltage level, 15 x 0. 0 = pin voltage level is low. 1 = pin voltage level is high. bit(s) type name description 31:16 reserved. 15 ro 1?bx gpio_din15 gpio15 pin voltage level. 14 ro 1?bx gpio_din14 gpio14 pin voltage level. 13:9 reserved. 8ro1?bxgpio_din8 gpio8 pin voltage level. 7ro1?bxgpio_din7 gpio7 pin voltage level. 6ro1?bxgpio_din6 gpio6 pin voltage level. 5ro1?bxgpio_din5 gpio5 pin voltage level. 4:0 reserved.
cx82100 home network processor data sheet 9-6 conexant proprietary and confidential information 101306c 9.3.6 gpio data input register 2 for gpio[31; 27:24; 22:16] (gpio_data_in2: 0x003500c4) gpio_data_in2 is the data input register for gpio[31; 27:24; 22:16]. bit(s) type default name description 15:0; 15 y 0, y = bit # ro 16?bx gpio_din {x}, 31 x 16, x = y + 16 gpio[x] pin voltage level, 31 x 16. 0 = pin voltage level is low. 1 = pin voltage level is high. bit(s) type name description 31:16 reserved. 15 ro 1?bx gpio_din31 gpio31 pin voltage level. 14:12 reserved. 11 ro 1?bx gpio_din27 gpio27 pin voltage level. 10 ro 1?bx gpio_din26 gpio26 pin voltage level. 9 reserved. 8ro1?bxgpio_din24 gpio24 pin voltage level. 7 reserved. 6ro1?bxgpio_din22 gpio22 pin voltage level. 5ro1?bxgpio_din21 gpio21 pin voltage level. 4ro1?bxgpio_din20 gpio20 pin voltage level. 3ro1?bxgpio_din19 gpio19 pin voltage level. 2ro1?bxgpio_din18 gpio18 pin voltage level. 1ro1?bxgpio_din17 gpio17 pin voltage level. 0ro1?bxgpio_din16 gpio16 pin voltage level. 9.3.7 gpio data input register 3 for gpio[39:37; 32] (gpio_data_in3: 0x003500c8) gpio_data_in3 is the data input register for gpio[39:37; 32]. bit(s) type default name description 7:0; 7 y 0, y = bit # ro 8?bx gpio_din {x}, 39 x 32, x = y + 32 gpio[x] pin voltage level, 39 x 32. 0 = pin voltage level is low. 1 = pin voltage level is high. bit(s) type name description 31:8 reserved. 7ro1?bxgpio_din39 gpio39 pin voltage level. 6ro1?bxgpio_din38 gpio38 pin voltage level. 5ro1?bxgpio_din37 gpio37 pin voltage level. 4:1 reserved. 0ro1?bxgpio_din32 gpio32 pin voltage level.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 9-7 9.3.8 gpio data output register 1 for gpio[15:14; 8:5] (gpio_data_out1: 0x003500cc) the gpio data output register 1 contains read/write data output bits and corresponding write-only output mask bits for gpio[15:14; 8:5]. writing a 1 to an output mask bit (gpio_domskx) enables the level corresponding to associated data output bit (gpio_doutx) onto the associated gpio pin when the associated direction bit (gpio_oex) is a 1; if the gpio_oex is a 0, there is no effect. writing a 0 to gpio_domskx has no effect. bit(s) type default name description 31:16; 31 y 16, y = bit # wo 16?b0 gpio_domsk{x}, 15 x 0, x = y-16 gpio[x] output mask, 15 x 0. read: reads a 0. write: gpio_dout[x] (bit y-16) mask (1 = enable; 0 = disable). 15:0; 15 y 0, y = bit # rw 16?bx gpio_dout{x}, 15 x 0, x = y gpio[x] data output, 15 x 0. read: reads the last value written to this bit. write: the output level (1 = high, 0 = low) is driven onto gpio[x] pin when mask bit is set (gpio_domsk[x] = 1) and signal direction is output (gpio_oe[x] = 1); no effect, otherwise. bit(s) type default name description 31 wo 1?b0 gpio_domsk15 gpio15 output mask. 30 wo 1?b0 gpio_domsk14 gpio14 output mask. 29:25 reserved. 24 wo 1?b1 gpio_domsk8 gpio8 output mask. 23 wo 1?b0 gpio_domsk7 gpio7 output mask. 22 wo 1?b0 gpio_domsk6 gpio6 output mask. 21 wo 1?b0 gpio_domsk5 gpio5 output mask. 20:16 reserved. 15 rw 1?bx gpio_dout15 gpio15 data output. 14 rw 1?bx gpio_dout14 gpio14 data output. 13:9 reserved. 8 rw 1?bx gpio_dout8 gpio8 data output. 7 rw 1?bx gpio_dout7 gpio7 data output. 6 rw 1?bx gpio_dout6 gpio6 data output. 5 rw 1?bx gpio_dout5 gpio5 data output. 4:0 reserved.
cx82100 home network processor data sheet 9-8 conexant proprietary and confidential information 101306c 9.3.9 gpio data output register 2 for gpio[31; 27:24; 22:16] (gpio_data_out2: 0x003500d0) the gpio data output register 2 contains read/write data output bits and corresponding write-only output mask bits for gpio[31; 27:24; 22:16]. writing a 1 to an output mask bit (gpio_domskx) enables the level corresponding to associated data output bit (gpio_doutx) onto the associated gpio pin when the associated direction bit (gpio_oex) is a 1; if the gpio_oex is a 0, there is no effect. writing a 0 to gpio_domskx has no effect. bit(s) type default name description 31:16; 31 y 16, y = bit # wo 16?b0 gpio_domsk{x}, 31 x 16, x = y gpio[x] output mask, 31 x 16. read: reads a 0. write: gpio_dout[x] (bit y-16) mask (1 = enable; 0 = disable). 15:0; 15 y 0, y = bit # rw 16?bx gpio_dout{x}, 31 x 16, x = y +16 gpio[x] data output, 31 x 16. read: reads the last value written to this bit. write: the output level (1 = high, 0 = low) is driven onto gpio[x] pin when mask bit is set (gpio_domsk[x] = 1) and signal direction is output (gpio_oe[x] = 1); no effect, otherwise. bit(s) type default name description 31 wo 1?b0 gpio_domsk31 gpio31 output mask. 30:28 reserved. 27 wo 1?b0 gpio_domsk27 gpio27 output mask. 26 wo 1?b0 gpio_domsk26 gpio26 output mask. 25 wo 1?b0 gpio_domsk25 gpio25 output mask. 24 wo 1?b0 gpio_domsk24 gpio24 output mask. 23 22 wo 1?b0 gpio_domsk22 gpio22 output mask. 21 wo 1?b0 gpio_domsk21 gpio21 output mask. 20 wo 1?b0 gpio_domsk20 gpio20 output mask. 19 wo 1?b0 gpio_domsk19 gpio19 output mask. 18 wo 1?b0 gpio_domsk18 gpio18 output mask. 17 wo 1?b1 gpio_domsk17 gpio17 output mask. 16 wo 1?b0 gpio_domsk16 gpio16 output mask. 15 rw - gpio_dout31 gpio31 data output. 14:12 reserved. 11 rw 1?bx gpio_dout27 gpio27 data output. 10 rw 1?bx gpio_dout26 gpio26 data output. 9 rw 1?bx gpio_dout25 gpio25 data output. 8 rw 1?bx gpio_dout24 gpio24 data output. 7 reserved. 6 rw 1?bx gpio_dout22 gpio22 data output. 5 rw 1?bx gpio_dout21 gpio21 data output. 4 rw 1?bx gpio_dout20 gpio20 data output. 3 rw 1?bx gpio_dout19 gpio19 data output. 2 rw 1?bx gpio_dout18 gpio18 data output. 1 rw 1?bx gpio_dout17 gpio17 data output. 0 rw 1?bx gpio_dout16 gpio16 data output.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 9-9 9.3.10 gpio data output register 3 for gpio[39:37; 32] (gpio_data_out3: 0x003500d4) the gpio data output register 3 contains read/write data output bits and corresponding write-only output mask bits for gpio[39:32]. writing a 1 to an output mask bit (gpio_domskx) enables the level corresponding to associated data output bit (gpio_doutx) onto the associated gpio pin when the associated direction bit (gpio_oex) is a 1; if the gpio_oex is a 0, there is no effect. writing a 0 to gpio_domskx has no effect. note: voltage levels for gpio[39:37; 32] pins assigned to special purpose functions by bits in the gpio_opt register are reflected in the gpio_data_in3 register, however, the gpio_data_out3 register bits are not applicable. bit(s) type default name description 31:24 reserved. 23:16; 23 y 16, y = bit # ro 8?b0 gpio_domsk{x}, 39 x 32, x = y+16 gpio[x] output mask, 39 x 32. read: reads a 0. write: gpio_dout[x] (bit y-=16) mask (1 = enable; 0 = disable). 15:8 reserved. 7:0; 7 y 0, y = bit # rw 8?bx gpio_dout{x}, 39 x 32, x = y+32 gpio[x] data output, 39 x 32. read: reads the last value written to this bit. write: the output level (1 = high, 0 = low) is driven onto gpio[x] pin when mask bit is set (gpio_domsk[x] = 1) and signal direction is output (gpio_oe[x] = 1); no effect, otherwise. bit(s) type default name description 31:24 reserved. 23 ro 1?b0 gpio_domsk39 gpio39 output mask. 22 ro 1?b0 gpio_domsk38 gpio38 output mask. 21 ro 1?b1 gpio_domsk37 gpio37 output mask. 20:17 reserved. 16 ro 1?b1 gpio_domsk32 gpio32 output mask. 15:8 reserved. 7 rw - gpio_dout39 gpio39 data output. 6 rw - gpio_dout38 gpio38 data output. 5 rw 1?b1 gpio_dout37 gpio37 data output. 4:1 reserved. 0 rw 1?b1 gpio_dout32 gpio32 data output.
cx82100 home network processor data sheet 9-10 conexant proprietary and confidential information 101306c 9.3.11 gpio interrupt status register 1 for gpio[15:14; 8:5] (gpio_isr1: 0x003500d8) gpio_isr1 is the interrupt input status register for gpio[15:14; 8:5]. note: if an interrupt is level-sensitive, the corresponding status bit will remain a 1 as long as the interrupt source is not removed. the status bit can be cleared only after the interrupt source is removed and a 1 is written to the bit. bit(s) type default name description 15:0; 15 y 0, y = bit # rr see specific bit gpio_is{x}, 15 x 0, x = y. gpio[x] interrupt status, 15 x 0. reading: bit #y = 0 = > no interrupt detected on gpio[x]. bit #y = 1 = > interrupt input detected on gpio[x]. writing: 0 to bit #y = > no effect 1 to bit #y = > clear the interrupt on gpio[x]. note: if the interrupt is level-sensitive, the status bit will remain a 1 as long as the interrupt resource is not removed. the bit can be cleared only after the resource is removed and a 1 is written to it. bit(s) type default name description 15 rr 1?b0 gpio_is15 gpio15 interrupt status. 14 rr 1?b0 gpio_is14 gpio14 interrupt status. 13:9 reserved. 8rr1?b0gpio_is8 gpio8 interrupt status. 7rr1?b0gpio_is7 gpio7 interrupt status. 6rr1?b0gpio_is6 gpio6 interrupt status. 5rr1?b0gpio_is5 gpio5 interrupt status. 4:0 reserved. 9.3.12 gpio interrupt status register 2 for gpio[31; 27:24; 22:16] (gpio_isr2: 0x003500dc) gpio_isr2 is the interrupt input status register for gpio[31; 27:16]. note: if an interrupt is level-sensitive, the corresponding status bit will remain a 1 as long as the interrupt source is not removed. the status bit can be cleared only after the interrupt source is removed and a 1 is written to the bit. bit(s) type default name description
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 9-11 bit(s) type default name description 15:0; 15 y 0, y = bit # rr see specific bit gpio_is{x}, 31 x 16, x = y+16. gpio[x] interrupt status, 31 x 16. reading: bit #y = 0 = > no interrupt detected on gpio[x]. bit #y = 1 = > interrupt input detected on gpio[x]. writing: 0 to bit #y = > no effect 1 to bit #y = > clear the interrupt on gpio[x]. note: if the interrupt is level-sensitive, the status bit will remain a 1 as long as the interrupt resource is not removed. the bit can be cleared only after the resource is removed and a 1 is written to it. bit(s) type default name description 15 rr 1?b0 gpio_is31 gpio31 interrupt status. 14:12 reserved. 11 rr 1?b0 gpio_is27 gpio27 interrupt status. 10 rr 1?b0 gpio_is26 gpio26 interrupt status. 9rr1?b0gpio_is25 gpio25 interrupt status. 8rr1?b0gpio_is24 gpio24 interrupt status. 7 reserved. 6rr1?b0gpio_is22 gpio22 interrupt status. 5rr1?b0gpio_is21 gpio21 interrupt status. 4rr1?b0gpio_is20 gpio20 interrupt status. 3rr1?b0gpio_is19 gpio19 interrupt status. 2rr1?b0gpio_is18 gpio18 interrupt status. 1rr1?b0gpio_is17 gpio17 interrupt status. 0rr1?b0gpio_is16 gpio16 interrupt status.
cx82100 home network processor data sheet 9-12 conexant proprietary and confidential information 101306c 9.3.13 gpio interrupt status register 3 for gpio[39:37; 32] (gpio_isr3: 0x003500e0) gpio_isr3 is the interrupt input status register for gpio[39:37; 32]. note: if an interrupt is level-sensitive, the corresponding status bit will remain a 1 as long as the interrupt source is not removed. the status bit can be cleared only after the interrupt source is removed and a 1 is written to the bit. bit(s) type default name description 7:0; 7 y 0, y = bit # rr see specific bit gpio_is{x}, 39 x 32, x = y+32. gpio[x] interrupt status, 39 x 32. reading: bit #y = 0 = > no interrupt detected on gpio[x]. bit #y = 1 = > interrupt input detected on gpio[x]. writing: 0 to bit #y = > no effect 1 to bit #y = > clear the interrupt on gpio[x]. note: if the interrupt is level-sensitive, the status bit will remain a 1 as long as the interrupt resource is not removed. the bit can be cleared only after the resource is removed and a 1 is written to it. bit(s) type default name description 31:8 reserved. 7rr1?b0gpio_is39 gpio39 interrupt status. 6rr1?b0gpio_is38 gpio38 interrupt status. 5rr1?b0gpio_is37 gpio37 interrupt status. 4:1 reserved. 0rr1?b0gpio_is32 gpio32 interrupt status.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 9-13 9.3.14 gpio interrupt enable register 1 for gpio[15:14; 8:5] (gpio_ier1: 0x003500e4) gpio_ier1 is the interrupt input enable register for gpio[15:14; 8:5]. note: if an interrupt input is enabled for gpio[x], then gpio[x] must be configured as an input. bit(s) type default name description 31:16; 31 y 16, y = bit # ro see specific bit gpio_iemsk{x}, 15 x 0, x = y-16. gpio[x] interrupt enable mask, 15 x 0. reading: return 0. writing: 0 = mask off the function associated with gpio_ie{x}. 1 = enable the function associated with gpio_ie{x}. 15:0; 15 y 0, y = bit # rw see specific bit gpio_ie{x}, 15 x 0, x = y. gpio[x] interrupt enable, 15 x 0. reading: return the last value written to bit #y. writing: 0 = disable the gpio[x] interrupt if gpio_iemsk{x} = 1; don't care, otherwise. 1 = enable the gpio[x] interrupt if gpio_iemsk{x} = 1; don't care, otherwise. bit(s) type default name description 31 ro 1?b0 gpio_iemsk15 gpio15 interrupt enable mask. 30 ro 1?b0 gpio_iemsk14 gpio14 interrupt enable mask. 29:25 reserved. 24 ro 1?b0 gpio_iemsk8 gpio8 interrupt enable mask. 23 ro 1?b0 gpio_iemsk7 gpio7 interrupt enable mask. 22 ro 1?b0 gpio_iemsk6 gpio6 interrupt enable mask. 21 ro 1?b0 gpio_iemsk5 gpio5 interrupt enable mask. 20:16 reserved. 15 rw 1?b0 gpio_ie15 gpio15 interrupt enable. 14 rw 1?b0 gpio_ie14 gpio14 interrupt enable. 13:9 reserved. 8rw1?b0gpio_ie8 gpio8 interrupt enable. 7rw1?b0gpio_ie7 gpio7 interrupt enable. 6rw1?b0gpio_ie6 gpio6 interrupt enable. 5rw1?b0gpio_ie5 gpio5 interrupt enable. 4:0 reserved.
cx82100 home network processor data sheet 9-14 conexant proprietary and confidential information 101306c 9.3.15 gpio interrupt enable register 2 for gpio[31; 27:24; 22:16] (gpio_ier2: 0x003500e8) gpio_ier2 is the interrupt input enable register for gpio[31:16]. note that if an interrupt input is enabled for gpio[x], then gpio[x] must be configured as an input. bit(s) type default name description 31:16; 31 y 16, y = bit # ro see specific bit gpio_iemsk{x}, 31 x 16, x = y. gpio[x] interrupt enable mask, 31 x 16. reading: return 0. writing: 0 to bit #y = > mask off the function associated with gpio_ie{x}. 1 to bit #y = > enable the function associated with gpio_ie{x}. 15:0; 15 y 0, y = bit # rw see specific bit gpio_ie{x}, 31 x 16, x = y+16. gpio[x] interrupt enable, 31 x 16. reading: return the last value written to bit #y. writing: 0 to bit #y = > disable the gpio[x] interrupt if gpio_iemsk{x} = 1; don't care, otherwise. 1 to bit #y = > enable the gpio[x] interrupt if gpio_iemsk{x} = 1; don't care, otherwise. bit(s) type default name description 31 ro 1?b0 gpio_iemsk31 gpio31 interrupt enable mask. 30:28 reserved. 27 ro 1?b0 gpio_iemsk27 gpio27 interrupt enable mask. 26 ro 1?b0 gpio_iemsk26 gpio26 interrupt enable mask. 25 ro 1?b0 gpio_iemsk25 gpio25 interrupt enable mask. 24 ro 1?b0 gpio_iemsk24 gpio24 interrupt enable mask. 23 reserved. 22 ro 1?b0 gpio_iemsk22 gpio22 interrupt enable mask. 21 ro 1?b0 gpio_iemsk21 gpio21 interrupt enable mask. 20 ro 1?b0 gpio_iemsk20 gpio20 interrupt enable mask. 19 ro 1?b0 gpio_iemsk19 gpio19 interrupt enable mask. 18 ro 1?b0 gpio_iemsk18 gpio18 interrupt enable mask. 17 ro 1?b0 gpio_iemsk17 gpio17 interrupt enable mask. 16 ro 1?b0 gpio_iemsk16 gpio16 interrupt enable mask. 15 ro 1?b0 gpio_ie31 gpio31 interrupt enable. 14:12 reserved. 11 rw 1?b0 gpio_ie27 gpio27 interrupt enable. 10 rw 1?b0 gpio_ie26 gpio26 interrupt enable. 9rw1?b0gpio_ie25 gpio25 interrupt enable. 8rw1?b0gpio_ie24 gpio24 interrupt enable. 7 reserved. 6rw1?b0gpio_ie22 gpio22 interrupt enable. 5rw1?b0gpio_ie21 gpio21 interrupt enable. 4rw1?b0gpio_ie20 gpio20 interrupt enable. 3rw1?b0gpio_ie19 gpio19 interrupt enable. 2rw1?b0gpio_ie18 gpio18 interrupt enable. 1rw1?b0gpio_ie17 gpio17 interrupt enable. 0rw1?b0gpio_ie16 gpio16 interrupt enable.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 9-15 9.3.16 gpio interrupt enable register 3 for gpio[39:37; 32] (gpio_ier3: 0x003500ec) gpio_ier3 is the interrupt input enable register for gpio[39:37; 32]. note: if an interrupt input is enabled for gpio[x], then gpio[x] must be configured as an input. bit(s) type default name description 31:24 reserved. 23:16; 23 y 16, y = bit # ro see specific bit gpio_iemsk{x}, 39 x 32, x = y+16. gpio[x] interrupt enable mask, 39 x 32. reading: return 0. writing: 0 to bit #y = > mask off the function associated with gpio_ie{x}. 1 to bit #y = > enable the function associated with gpio_ie{x}. 15:8 reserved. 7:0; 7 y 0, y = bit # rw see specific bit gpio_ie{x}, 39 x 32, x = y+32. gpio[x] interrupt enable, 39 x 32. reading: return the last value written to bit #y. writing: 0 to bit #y = > disable the gpio[x] interrupt if gpio_iemsk{x} = 1; don't care, otherwise. 1 to bit #y = > enable the gpio[x] interrupt if gpio_iemsk{x} = 1; don't care, otherwise. bit(s) type default name description 31:24 reserved. 23 ro 1?b0 gpio_iemsk39 gpio39 interrupt enable mask. 22 ro 1?b0 gpio_iemsk38 gpio38 interrupt enable mask. 21 ro 1?b0 gpio_iemsk37 gpio37 interrupt enable mask. 20:17 reserved. 16 ro 1?b0 gpio_iemsk32 gpio32 interrupt enable mask. 15:8 reserved. 7rw1?b0gpio_ie39 gpio39 interrupt enable. 6rw1?b0gpio_ie38 gpio38 interrupt enable. 5rw1?b0gpio_ie37 gpio37 interrupt enable. 4:1 reserved. 0rw1?b0gpio_ie32 gpio32 interrupt enable.
cx82100 home network processor data sheet 9-16 conexant proprietary and confidential information 101306c 9.3.17 gpio interrupt polarity control register 1 for gpio[15:14; 8:5] (gpio_ipc1: 0x003500f0) gpio_ipc1 is the interrupt polarity control register for gpio[15:14; 8:5]. bit(s) type default name description 31:16; 31 y 16, y = bit # ro see specific bit gpio_ipmsk{x}, 15 x 0, x = y-16. gpio[x] interrupt polarity mask, 15 x 0. reading: return 0. writing: 0 = mask off the function associated with gpio_ip{x}. 1 = enable the function associated with gpio_ip{x}. 15:0; 15 y 0, y = bit # rw see specific bit gpio_ip{x}, 15 x 0, x = y. gpio[x] interrupt polarity control, 15 x 0. reading: return the last value written to bit #y. writing: 1 = for gpio_ipmsk{x} = 1, interrupt will occur upon gpio[x] high or positive edge; for gpio_ipmsk{x} = 0, interrupt will not occur upon gpio[x] high or positive edge. 0 = for gpio_ipmsk{x} = 1, interrupt will occur upon gpio[x] low or negative edge; for gpio_ipmsk{x} = 0, interrupt will not occur upon gpio[x] low or negative edge. bit(s) type default name description 31 ro 1?b0 gpio_ipmsk15 gpio15 interrupt polarity mask. 30 ro 1?b0 gpio_ipmsk14 gpio14 interrupt polarity mask. 29:25 reserved. 24 ro 1?b0 gpio_ipmsk8 gpio8 interrupt polarity mask. 23 ro 1?b0 gpio_ipmsk7 gpio7 interrupt polarity mask. 22 ro 1?b0 gpio_ipmsk6 gpio6 interrupt polarity mask. 21 ro 1?b0 gpio_ipmsk5 gpio5 interrupt polarity mask. 20:16 reserved. 15 rw 1?b0 gpio_ip15 gpio15 interrupt polarity control. 14 rw 1?b0 gpio_ip14 gpio14 interrupt polarity control. 13:9 reserved. 8rw1?b0gpio_ip8 gpio8 interrupt polarity control. 7rw1?b0gpio_ip7 gpio7 interrupt polarity control. 6rw1?b0gpio_ip6 gpio6 interrupt polarity control. 5rw1?b0gpio_ip5 gpio5 interrupt polarity control. 4:0 reserved.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 9-17 9.3.18 gpio interrupt polarity control register 2 for gpio[31; 27:24; 22:16] (gpio_ipc2: 0x003500f4) gpio_ipc2 is the interrupt polarity control register for gpio[31; 27:24; 22:16]. bit(s) type default name description 31:16; 31 y 16, y = bit # ro see specific bit gpio_ipmsk{x}, 31 x 16, x = y. gpio[x] interrupt polarity mask, 31 x 16. reading: return 0. writing: 0 = mask off the function associated with gpio_ip{x}. 1 = enable the function associated with gpio_ip{x}. 15:0; 15 y 0, y = bit # rw see specific bit gpio_ip{x}, 31 x 16, x = y+16. gpio[x] interrupt polarity control, 31 x 16. reading: return the last value written to bit #y. writing: 1 = for gpio_ipmsk{x} = 1, interrupt will occur upon gpio[x] high or positive edge; for gpio_ipmsk{x} = 0, interrupt will not occur upon gpio[x] high or positive edge. 0 = for gpio_ipmsk{x} = 1, interrupt will occur upon gpio[x] low or negative edge; for gpio_ipmsk{x} = 0, interrupt will not occur upon gpio[x] low or negative edge. bit(s) type default name description 31 ro 1?b0 gpio_ipmsk31 gpio31 interrupt polarity mask. 30:28 reserved. 27 ro 1?b0 gpio_ipmsk27 gpio27 interrupt polarity mask. 26 ro 1?b0 gpio_ipmsk26 gpio26 interrupt polarity mask. 25 ro 1?b0 gpio_ipmsk25 gpio25 interrupt polarity mask. 24 ro 1?b0 gpio_ipmsk24 gpio24 interrupt polarity mask. 23 reserved. 22 ro 1?b0 gpio_ipmsk22 gpio22 interrupt polarity mask. 21 ro 1?b0 gpio_ipmsk21 gpio21 interrupt polarity mask. 20 ro 1?b0 gpio_ipmsk20 gpio20 interrupt polarity mask. 19 ro 1?b0 gpio_ipmsk19 gpio19 interrupt polarity mask. 18 ro 1?b0 gpio_ipmsk18 gpio18 interrupt polarity mask. 17 ro 1?b0 gpio_ipmsk17 gpio17 interrupt polarity mask. 16 ro 1?b0 gpio_ipmsk16 gpio16 interrupt polarity mask. 15 rw 1?b0 gpio_ip31 gpio31 interrupt polarity control. 14:12 reserved. 11 rw 1?b0 gpio_ip27 gpio27 interrupt polarity control. 10 rw 1?b0 gpio_ip26 gpio26 interrupt polarity control. 9rw1?b0gpio_ip25 gpio25 interrupt polarity control. 8rw1?b0gpio_ip24 gpio24 interrupt polarity control. 7 reserved. 6rw1?b0gpio_ip22 gpio22 interrupt polarity control. 5rw1?b0gpio_ip21 gpio21 interrupt polarity control. 4rw1?b0gpio_ip20 gpio20 interrupt polarity control. 3rw1?b0gpio_ip19 gpio19 interrupt polarity control. 2rw1?b0gpio_ip18 gpio18 interrupt polarity control. 1rw1?b0gpio_ip17 gpio17 interrupt polarity control. 0rw1?b0gpio_ip16 gpio16 interrupt polarity control.
cx82100 home network processor data sheet 9-18 conexant proprietary and confidential information 101306c 9.3.19 gpio interrupt polarity control register 3 for gpio[39:37; 32] (gpio_ipc3: 0x003500f8) gpio_ipc3 is the interrupt polarity control register for gpio[39:37; 32]. bit(s) type default name description 31:24 reserved. 23:16; 23 y 16, y = bit # ro see specific bit gpio_ipmsk{x}, 39 x 32, x = y+16. gpio[x] interrupt polarity mask, 39 x 32. reading: return 0. writing: 0 = mask off the function associated with gpio_ip{x}. 1 = enable the function associated with gpio_ip{x}. 15:8 reserved. 7:0; 7 y 0, y = bit # rw see specific bit gpio_ip{x}, 39 x 32, x = y+32. gpio[x] interrupt polarity control, 39 x 32. reading: return the last value written to bit #y. writing: 1 = for gpio_ipmsk{x} = 1, interrupt will occur upon gpio[x] high or positive edge; for gpio_ipmsk{x} = 0, interrupt will not occur upon gpio[x] high or positive edge. 0 = for gpio_ipmsk{x} = 1, interrupt will occur upon gpio[x] low or negative edge; for gpio_ipmsk{x} = 0, interrupt will not occur upon gpio[x] low or negative edge. bit(s) type default name description 31:24 reserved. 23 ro 1?b0 gpio_ipmsk39 gpio39 interrupt polarity mask. 22 ro 1?b0 gpio_ipmsk38 gpio38 interrupt polarity mask. 21 ro 1?b0 gpio_ipmsk37 gpio37 interrupt polarity mask. 20:17 reserved. 16 ro 1?b0 gpio_ipmsk32 gpio32 interrupt polarity mask. 15:8 reserved. 7rw1?b0gpio_ip39 gpio39 interrupt polarity control. 6rw1?b0gpio_ip38 gpio38 interrupt polarity control. 5rw1?b0gpio_ip37 gpio37 interrupt polarity control. 4:1 reserved. 0rw1?b0gpio_ip32 gpio32 interrupt polarity control.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 9-19 9.3.20 gpio interrupt sensitivity mode register 1 for gpio[15:14; 8:5] (gpio_ism1: 0x003500a0) gpio_ism1 is the interrupt sensitive mode register for gpio[15:14; 8:5]. bit(s) type default name description 31:16; 31 y 16, y = bit # ro see specific bit gpio_ismmsk{x}, 15 x 0, x = y-16. gpio[x] interrupt sensitivity mode mask, 15 x 0. reading: return 0. writing: 0= mask off the function associated with gpio_ismc{x}. 1 = enable the function associated with gpio_ismc{x}. 15:0; 15 y 0, y = bit # rw see specific bit gpio_ismc{x}, 15 x 0, x = y. gpio[x] interrupt sensitivity mode control, 15 x 0. reading: return the last value written to bit #y. writing: 1 = interrupt input on gpio[x] will be edge sensitive, if gpio_ismmsk{x} = 1; don't care, otherwise. 0 = interrupt input on gpio[x] will be level sensitive, if gpio_ismmsk{x} = 1; don't care, otherwise. bit(s) type default name description 31 ro 1?b0 gpio_ismmsk15 gpio15 interrupt sensitivity mode mask. 30 ro 1?b0 gpio_ismmsk14 gpio14 interrupt sensitivity mode mask. 29:25 reserved. 24 ro 1?b0 gpio_ismmsk8 gpio8 interrupt sensitivity mode mask. 23 ro 1?b0 gpio_ismmsk7 gpio7 interrupt sensitivity mode mask. 22 ro 1?b0 gpio_ismmsk6 gpio6 interrupt sensitivity mode mask. 21 ro 1?b0 gpio_ismmsk5 gpio5 interrupt sensitivity mode mask. 20:16 reserved. 15 rw 1?b0 gpio_ismc15 gpio15 interrupt sensitivity mode control. 14 rw 1?b0 gpio_ismc14 gpio14 interrupt sensitivity mode control. 13:9 reserved. 8rw1?b0gpio_ismc8 gpio8 interrupt sensitivity mode control. 7rw1?b0gpio_ismc7 gpio7 interrupt sensitivity mode control. 6rw1?b0gpio_ismc6 gpio6 interrupt sensitivity mode control. 5rw1?b0gpio_ismc5 gpio5 interrupt sensitivity mode control. 4:0 reserved.
cx82100 home network processor data sheet 9-20 conexant proprietary and confidential information 101306c 9.3.21 gpio interrupt sensitivity mode register 2 for gpio[31; 27:24; 22:16] (gpio_ism2: 0x003500a4) gpio_ism2 is the interrupt sensitive mode register for gpio[31; 27:24; 22:16]. bit(s) type default name description 31:16; 31 y 16, y = bit # ro see specific bit gpio_ismmsk{x}, 31 x 16, x = y. gpio[x] interrupt sensitivity mode mask, 31 x 16. reading: return 0. writing: 0= mask off the function associated with gpio_ismc{x}. 1 = enable the function associated with gpio_ismc{x}. 15:0; 15 y 0, y = bit # rw see specific bit gpio_ismc{x}, 31 x 16, x = y+16. gpio[x] interrupt sensitivity mode control, 31 x 16. reading: return the last value written to bit #y. writing: 1 = interrupt input on gpio[x] will be edge sensitive, if gpio_ismmsk{x} = 1; don't care, otherwise. 0 = interrupt input on gpio[x] will be level sensitive, if gpio_ismmsk{x} = 1; don't care, otherwise. bit(s) type default name description 31 ro 1?b0 gpio_ismmsk31 gpio31 interrupt sensitivity mode mask. 30:28 reserved. 27 ro 1?b0 gpio_ismmsk27 gpio27 interrupt sensitivity mode mask. 26 ro 1?b0 gpio_ismmsk26 gpio26 interrupt sensitivity mode mask. 25 ro 1?b0 gpio_ismmsk25 gpio25 interrupt sensitivity mode mask. 24 ro 1?b0 gpio_ismmsk24 gpio24 interrupt sensitivity mode mask. 23 reserved. 22 ro 1?b0 gpio_ismmsk22 gpio22 interrupt sensitivity mode mask. 21 ro 1?b0 gpio_ismmsk21 gpio21 interrupt sensitivity mode mask. 20 ro 1?b0 gpio_ismmsk20 gpio20 interrupt sensitivity mode mask. 19 ro 1?b0 gpio_ismmsk19 gpio19 interrupt sensitivity mode mask. 18 ro 1?b0 gpio_ismmsk18 gpio18 interrupt sensitivity mode mask. 17 ro 1?b0 gpio_ismmsk17 gpio17 interrupt sensitivity mode mask. 16 ro 1?b0 gpio_ismmsk16 gpio16 interrupt sensitivity mode mask. 15 rw 1?b0 gpio_ismc31 gpio31 interrupt sensitivity mode control. 14 rw 1?b0 gpio_ismc30 gpio30 interrupt sensitivity mode control. 13 rw 1?b0 gpio_ismc29 gpio29 interrupt sensitivity mode control. 12 rw 1?b0 gpio_ismc28 gpio28 interrupt sensitivity mode control. 11 rw 1?b0 gpio_ismc27 gpio27 interrupt sensitivity mode control. 10 rw 1?b0 gpio_ismc26 gpio26 interrupt sensitivity mode control. 9rw1?b0gpio_ismc25 gpio25 interrupt sensitivity mode control. 8rw1?b0gpio_ismc24 gpio24 interrupt sensitivity mode control. 7rw1?b0gpio_ismc23 gpio23 interrupt sensitivity mode control. 6rw1?b0gpio_ismc22 gpio22 interrupt sensitivity mode control. 5rw1?b0gpio_ismc21 gpio21 interrupt sensitivity mode control. 4rw1?b0gpio_ismc20 gpio20 interrupt sensitivity mode control. 3rw1?b0gpio_ismc19 gpio19 interrupt sensitivity mode control. 2rw1?b0gpio_ismc18 gpio18 interrupt sensitivity mode control. 1rw1?b0gpio_ismc17 gpio17 interrupt sensitivity mode control. 0rw1?b0gpio_ismc16 gpio16 interrupt sensitivity mode control.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 9-21 9.3.22 gpio interrupt sensitivity mode register 3 for gpio[39:37; 32] (gpio_ism3: 0x003500a8) gpio_ism2 is the interrupt sensitive mode register for gpio[39:37; 32]. bit(s) type default name description 31:24 reserved. 23:16; 23 y 16, y = bit # ro see specific bit gpio_ismmsk{x}, 39 x 32, x = y+16. gpio[x] interrupt sensitivity mode mask, 39 x 32. reading: return 0. writing: 0= mask off the function associated with gpio_ismc{x}. 1 = enable the function associated with gpio_ismc{x}. 15:8 reserved. 7:0; 7 y 0, y = bit # rw see specific bit gpio_ismc{x}, 39 x 32, x = y+32. gpio[x] interrupt sensitivity mode control, 39 x 32. reading: return the last value written to bit #y. writing: 1 = interrupt input on gpio[x] will be edge sensitive, if gpio_ismmsk{x} = 1; don't care, otherwise. 0 = interrupt input on gpio[x] will be level sensitive, if gpio_ismmsk{x} = 1; don't care, otherwise. bit(s) type default name description 31:24 reserved. 23 ro 1?b0 gpio_ismmsk39 gpio39 interrupt sensitivity mode mask. 22 ro 1?b0 gpio_ismmsk38 gpio38 interrupt sensitivity mode mask. 21 ro 1?b0 gpio_ismmsk37 gpio37 interrupt sensitivity mode mask. 20:17 reserved. 16 ro 1?b0 gpio_ismmsk32 gpio32 interrupt sensitivity mode mask. 15:8 reserved. 7rw1?b0gpio_ismc39 gpio39 interrupt sensitivity mode control. 6rw1?b0gpio_ismc38 gpio38 interrupt sensitivity mode control. 5rw1?b0gpio_ismc37 gpio37 interrupt sensitivity mode control. 4:1 reserved. 0rw1?b0gpio_ismc32 gpio32 interrupt sensitivity mode control.
cx82100 home network processor data sheet 9-22 conexant proprietary and confidential information 101306c this page is intentionally blank.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 10-1 10 memory to memory transfer input/output 10.1 operation a qword buffer resides within this block to support memory to memory block transfers. data transfer requests are issued to the dmac via channel 7 for reading from the source buffer and channel 8 for writing to the destination buffer. the number of qwords to transfer is set by m2m_cntl. this count is big enough to initialize the entire 8 mb of external sdram if desired. when m2m_cntl is set to 0, or counts down to 0, the dma block transfer is done. an interrupt is set (int_stat:8) when the dmac completes the data block transfer. if m2m_do is set, then only write transfers will occur to the destination buffer. since the arm can also write to the dma port buffer m2m_dma, it could use the dmac to initialize memory to any constant. the memory-to-memory transfer always consists of an integer number of qwords. the source and destination addresses are always dword-aligned. little-endian byte- realignment is supported by using m2m_bs and using firmware for cleaning up the end conditions. some examples for m2m data transfers are shown in table 10-1, table 10-2, and table 10-3. the bytes highlighted in bold have to be copied or restored by firmware. table 10-1. m2m transfer example 1 m2m data transfer example source memory to copy: 24b destination memory after copy m2m_cnt = 3 qwords, dma8_ptr1 = 00 start source byte-address start destination byte-address 0 1 2 3 m2m_bs, dma7_ptr1 byte address 0 destination memory before copy 0, 00 1, 00 2, 00 3, 00 00 03020100 ffffffff 03020100 020100 xx 0100 xxxx 00 xxxxxx 04 07060504 ffffffff 07060504 06050403 05040302 04030201 08 0b0a0908 ffffffff 0b0a0908 0a090807 09080706 08070605 0c 0f0e0d0c ffffffff 0f0e0d0c 0e0d0c0b 0d0c0b0a 0c0b0a09 10 13121110 ffffffff 13121110 1211100f 11100f0e 100f0e0d 14 17161514 ffffffff 17161514 16151413 15141312 14131211 18 1b1a1918 ffffffff ffffffff ffffff ff ffff ffff ff ffffff
cx82100 home network processor data sheet 10-2 conexant proprietary and confidential information 101306c table 10-2. m2m transfer example 2 m2m data transfer example source memory to copy: 24b destination memory after copy m2m_cnt = 3 qwords, dma8_ptr1 = 00 start source byte-address start destination byte-address 0 1 2 3 m2m_bs, dma7_ptr1 byte address 1 destination memory before copy 3, 04 0, 00 1, 00 2, 00 00 030201 00 ffffffff 04 xxxxxx 030201 00 0201 00xx 01 00xxxx 04 07060504 ffffffff 08070605 07060504 06050403 05040302 08 0b0a0908 ffffffff 0c0b0a09 0b0a0908 0a090807 09080706 0c 0f0e0d0c ffffffff 100f0e0d 0f0e0d0c 0e0d0c0b 0d0c0b0a 10 13121110 ffffffff 14131211 13121110 1211100f 11100f0e 14 17161514 ffffffff 18171615 17161514 16151413 15141312 18 1b1a19 18 ffffffff ffffffff ffffff ff ffff ffff ff ffffff table 10-3. m2m transfer example 3 m2m data transfer example source memory to copy: 24b destination memory after copy m2m_cnt = 3 qwords, dma8_ptr1 = 00 start source byte-address start destination byte-address 0 1 2 3 m2m_bs, dma7_ptr1 byte address 3 destination memory before copy 1, 04 2, 04 3, 04 0, 00 00 03 020100 ffffffff 060504 xx 0504 xxxx 04 xxxxxx 03 020100 04 07060504 ffffffff 0a090807 09080706 08070605 07060504 08 0b0a0908 ffffffff 0e0d0c0b 0d0c0b0a 0c0b0a09 0b0a0908 0c 0f0e0d0c ffffffff 1211100f 11100f0e 100f0e0d 0f0e0d0c 10 13121110 ffffffff 16151413 15141312 14131211 13121110 14 17161514 ffffffff 1a191817 19181716 18171615 17161514 18 1b 1a1918 ffffffff ffffffff ffffff ff ffff ffff ff ffffff when doing a multiple qword buffer transfer there are actually 128 cases to consider for byte re-alignment. this # of permutations results from 4 start byte src-locations, 8 end byte src-locations, and 4 start byte dst-locations (4x8x4 = 128). the start/end src- locations bound the buffer size for transfer. the firmware will need to fix the corrupted first dword (save original dst-1 st -loc before copy), and also supply the last byte-merged 1- 2 dwords.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 10-3 10.2 m2m register memory map m2m registers are identified in table 10-4 table 10-4. m2m registers register label register name asb address type default value ref. m2m_dma memory to memory dma data register 0x00350000 rwp 64?bx 10.3.1 m2m_cntl memory to memory dma transfer control/counter 0x00350004 rw 0x00000000 10.3.2 10.3 m2m registers 10.3.1 memory to memory dma data register (m2m_dma: 0x00350000) bit(s) type default name description 63:0 rwp 64?bx m2m_dma a single qword buffer for dma source/destination access. 10.3.2 memory to memory dma transfer control/counter (m2m_cntl: 0x00350004) bit(s) type default name description 22:21 rw 2?b0 m2m_bs memory to memory bytes to lag data or shift left. no. of bytes to lag data or shift left. useful for little-endian byte re-alignment. 20 rw 1?b0 m2m_do disabled memory to memory source transfers. 0 = enable source and destination transfers. 1 = disable source transfers, and enable only destination transfers. 19:0 rw 20?b0 m2m_cnt memory to memory count. no. of qwords to transfer.
cx82100 home network processor data sheet 10-4 conexant proprietary and confidential information 101306c this page is intentionally blank.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 11-1 11 interrupt controller interface description all peripheral interrupt sources are routed through the interrupt controller (intc) and reduced to one of two active low inputs to the arm940t processor, fast interrupt (fiq#) or regular interrupt (irq#), as selected in the interrupt level assignment register (int_la). no hardware-assisted priority scheme is implemented in the hnp other than fiq# having a higher priority than irq#. the system software must implement the priority scheme for individual interrupts in the fiq# and irq# exception handlers. 11.1 intc register memory map intc registers are identified in table 11-1. table 11-1. intc registers register label register name asb address type default value ref. int_la interrupt level assignment register 0x00350040 rw 0x00000000 11.2.1 int_stat interrupt status register 0x00350044 rr 0x00000000 11.2.2 int_setstat interrupt set status register 0x00350048 wo 0x00000000 11.2.3 int_msk interrupt mask register 0x0035004c rw 0x00000000 11.2.4 int_mstat interrupt mask status register 0x00350090 ro 0x00000000 11.2.5 11.2 intc registers 11.2.1 interrupt level assignment register (int_la: 0x00350040) the intc receives an interrupt signal from a potential interrupt source and compares it with the corresponding interrupt level assignment register (int_la) to determine if a fast interrupt (fiq#) signal or a regular interrupt (irq#) signal should be sent to the arm940t processor. setting the interrupt's corresponding bit on the interrupt level assignment register to a 1 will cause a fiq# interrupt, while a 0 will cause an irq# interrupt. bit type default name description 31:0 rw 32?h00000000 int_la_x level assignment interrupt control. 0 = the corresponding bit location in the int_stat register will cause an irq# interrupt to the intc if the interrupt has been enabled. 1 = the corresponding bit location in the int_stat register will cause a fiq# interrupt to the intc if the interrupt has been enabled.
cx82100 home network processor data sheet 11-2 conexant proprietary and confidential information 101306c 11.2.2 interrupt status register (int_stat: 0x00350044) each interrupt source sets a bit in the interrupt status register (int_stat). these pending interrupts can be read at anytime. if a bit in this register represents multiple interrupt sources, then it is read-only. most bits are automatically cleared once all the corresponding interrupt sources are cleared, however, bits 19 and 20 are not automatically cleared. any other bit in this register can be cleared by writing a one to the same bit location. (note that in some cases, the interrupt source in the peripheral must be cleared before the clearing of the corresponding interrupt bit in this register can take effect.). writing a zero has no effect. bit type default name description 31 rr 1?b0 int_sw3 software interrupt 3. 0 = interrupt condition has not occurred. 1 = the corresponding data bit has been set high when writing to int_setstat. 30 rr 1?b0 int_sw2 software interrupt 2. 0 = interrupt condition has not occurred. 1 = the corresponding data bit has been set high when writing to int_setstat. 29 rr 1?b0 int_sw1 software interrupt 1. 0 = interrupt condition has not occurred. 1 = the corresponding data bit has been set high when writing to int_setstat. 28 rr 1?b0 int_sw0 software interrupt 0. 0 = interrupt condition has not occurred. 1 = the corresponding data bit has been set high when writing to int_setstat. 27 rr 1?b0 int_commrx arm9 communication rxd channel interrupt. 0 = the receive buffer does not contain data waiting to be read. 1 = the arm9 communication rxd channel (between processor and the debugger) receive buffer contains data waiting to be read. 26 rr 1?b0 int_commtx arm9 communication txd channel interrupt. 0 = the transmit buffer is not empty. 1 = the arm9 communication txd channel (between processor and the debugger) transmit buffer is empty. 25 reserved. 24 ro 1?b0 int_gpio gpio interrupt. 0 = interrupt condition has not occurred. 1 = an external interrupt through a gpio input pin has occurred. 23:21 reserved. 20 rr 1?b0 int_emac#2_err emac 2 exception condition interrupt. 0 = interrupt condition has not occurred. 1 = emac 2 receiver or transmitter detected a normal or abnormal exception condition. must be written to be cleared. 19 rr 1?b0 int_emac#1_err emac 1 exception condition interrupt. 0 = interrupt condition has not occurred. 1 = emac 1 receiver or transmitter detected a normal or abnormal exception condition. must be written to be cleared.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 11-3 bit type default name description 18 rr 1?b0 int_dmac_err dmac berror interrupt 0 = interrupt condition has not occurred. 1 = the berror signal has been asserted to the dmac asb master. 17:16 reserved. 15 rr 1?b0 int_dmac_emac#1_tx dma channel 1 transfer complete interrupt. 0 = interrupt condition has not occurred. 1 = dmac completed a block/packet transfer to emac 1. 14 rr 1?b0 int_dmac_emac#1_rx dma channel 2 transfer complete interrupt. 0 = interrupt condition has not occurred. 1 = dmac completed a block/packet transfer from emac 1. 13 rr 1?b0 int_dmac_emac#2_tx dma channel 3 transfer complete interrupt. 0 = interrupt condition has not occurred. 1 = dmac completed a block/packet transfer to emac 2. 12 rr 1?b0 int_dmac_emac#2_rx dma channel 4 transfer complete interrupt. 0 = interrupt condition has not occurred. 1 = dmac completed a block/packet transfer from emac 2. 11:9 reserved. 8 rr 1?b0 int_m2m_dst dma channel 8 transfer complete interrupt. 0 = interrupt condition has not occurred. 1 = memory-to-memory transfer is complete. 7rr 1?b0int_host_err host bus error interrupt. 0 = interrupt condition has not occurred. 1 = the external host encountered a bus error while mastering the asb. 6rr 1?b0int_host host write interrupt. 0 = interrupt condition has not occurred. 1 = the external host wrote to the h_int bit in the host status/control register. 5 reserved. 4 ro 1?b0 int_usb usb interrupt. 0 = interrupt condition has not occurred. 1 = there is a usb interrupt pending. 3rr 1?b0int_timer4 timer 4 interrupt. 0 = interrupt condition has not occurred. 1 = timer 4 current count reached the limit value. 2rr 1?b0int_timer3 timer 3 interrupt. 0 = interrupt condition has not occurred. 1 = timer 3 current count reached the limit value. 1rr 1?b0int_timer2 timer 2 interrupt. 0 = interrupt condition has not occurred. 1 = timer 2 current count reached the limit value. 0rr 1?b0int_timer1 timer 1 interrupt. 0 = interrupt condition has not occurred. 1 = timer 1 current count reached the limit value.
cx82100 home network processor data sheet 11-4 conexant proprietary and confidential information 101306c 11.2.3 interrupt set status register (int_setstat: 0x00350048) this is a write-only register. the interrupt set status (int_setstat) register has 32 bits. writing a one to a bit location of this register will cause the corresponding interrupt to occur. writing a zero will have no effect. only the four software interrupts defined in int_stat[31:28] can be triggered by using this register. bit type default name description 31:28 wo 4?b0 int_setstat_x interrupt set status control. 0 = no effect. 1 = forces an interrupt to the intc if the corresponding bit location in the int_msk register is enabled. will cause the corresponding bit in the int_stat register to be set. 27:0 reserved. 11.2.4 interrupt mask register (int_msk: 0x0035004c) the pending interrupts are masked (anded) with the interrupt mask register (int_msk) before being logically ored to the arm interrupt input. the int_msk register has 32 bits. writing a one to a bit location of this register will enable the corresponding interrupt in int_stat. writing a zero to a bit location of this register will disable the interrupt. the enabled or active interrupts are also readable at register int_mstat. bit type default name description 31:0 rw 32?h00000000 int_msk_x interrupt mask (enable) control. 0 = interrupts on the corresponding bit location in the int_stat register are disabled. 1 = interrupts on the corresponding bit location in the int_stat register are enabled. 11.2.5 interrupt mask status register (int_mstat: 0x00350090) this is a read-only register. it is logically equivalent to the and of int_stat and int_msk registers. it provides a convenient way for software to determine which interrupts have occurred. bit type default name description 31:0 ro 32?h00000000 int_mstat_x interrupt mask status. 0 = interrupts has not occurred on the corresponding bit location in the int_stat register. 1 = interrupts has occurred on the corresponding bit location in the int_stat register.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 12-1 12 timers interface description 12.1 programmable periodic timers there are four programmable timers (timer 1?timer 4) available for real-time interrupts with a normal range from 1 s to 65 ms. timer 3 can also be used as a system watchdog timer. the timers are based on 16-bit counters that increment at a 1.0 mhz rate. the 1.0 mhz rate is based upon pclk and pll_b register bits pll_b_cr. table 13-6 shows the bclk clock frequencies for which the 1.0 mhz rate is guaranteed. if the pll_b frequency is not programmed to the listed values, the timers will not run at 1.0 mhz. see section 12 for more information. each timer?s counter register (tm_cnt{x}) is reset to 0 when its limit register (tm_lmt{x}) is written. each timer?s tm_cnt register increments from 0 up to the limit value programmed in its tm_lmt register. when the counter reaches the limit value, the counter resets back to 0 and sets its corresponding interrupt status bit (int_timer{x} ? see section 11.2.2). an interrupt to the arm940t processor will then occur if the corresponding interrupt enable bit is set in the interrupt mask register (int_msk[3:0]. the counters continue to increment during the pending interrupts. if tm_lmt{x} is set to 0, tm_cnt{x} stays reset, does not increment, and therefore never causes an interrupt. as an example, a 50 ms periodic real-time interrupt can be achieved by setting tm_lmt{x} to 16?hc34f. 12.2 watchdog timer a system watchdog is implemented via a special case of timer 3. the timer counts up to tm_lmt3. when reached it sets the int_tm3 interrupt. this normal operation, like the other two timers, produces an int_tm3 interrupt every (1 + tm_lmt3) s. unlike the other timers, if tm_lmt3[3:0] is written with a value of 1?hf, watchdog mode is enabled. this particular nibble of tm_lmt3 causes tm_lmt3 to not be able to be changed (i.e., writes will have no effect) until after the next system reset. it also causes an internal 7-bit counter to increment after every int_timer3 event. if this counter is not cleared by writing tm_lmt3 with any value (this does not affect tm_lmt3 after initial programming) before the 7-bit counter reaches 100, a global reset will take effect, which is the same in effect as asserting the hrst# pin. the watchdog function is ?re-armed? after each clear, i.e., the 7-bit counter is reset to 0 after each write to tm_lmt3. once enabled, it cannot be disabled other than by a global reset. for example, if tm_lmt3 is programmed to 16?h61a7, then a normal int_timer3 interrupt occurs every 25 ms and the watchdog function is not enabled. if tm_lmt3 is programmed to 16?h270f, then an int_timer3 interrupt occurs every 10 ms and the watchdog function of timer 3 is enabled. the 7-bit counter must be cleared by writing to tm_lmt3 before a timeout of 1 sec occurs, otherwise the global reset will occur.
cx82100 home network processor data sheet 12-2 conexant proprietary and confidential information 101306c 12.3 timer usage/sdram refresh with other frequencies normal hnp operation assumes bclk is 25, 50, 62.5, 75, or 100 mhz (see section 13.1). the timer resolution circuitry and sdram refresh rates are based upon these frequencies. however, if a different frequency is desired, the resolution of the timer and sdram refresh rates are based on parameter values listed in table 12-1. table 12-1. timer resolution and sdram refresh rate bclk speed select (pll_b_cr_slow) epclk clock rate select (pll_b_cr) resolution sdram refresh rate notes 0 (normal) 00 ( 3) pclk/37.5 bclk/900 0 (normal) 01 ( 4) pclk/50 bclk/1200 0 (normal) 10 ( 5) pclk/62.5 bclk/1500 1 (slow) 00 ( 1) pclk/12.5 bclk/300 default at por 1 (slow) 01 ( 2) pclk/25 bclk/600 sdrams typically require refresh rates at approximately 15.6 s or faster. normal hnp operation, when configuring bclk as in section 13.1, achieves a refresh rate of 12 s. care must be taken to avoid use of a refresh rate that is too slow. if the refresh rate is too fast, application performance could be reduced. a normal example is that bclk is programmed for 100 mhz, with pll_b_cr_slow = 0 and pll_b_cr = 01. pclk would then be 50 mhz, epclk would then be 25 mhz, and the timer resolution would be 50/50 mhz, which is equal to 1 s. the sdram refresh rate would be 100 mhz/1200, which is equal to 12 s. an example using a different bclk frequency is bclk programmed to be 80 mhz, with pll_b_cr_slow = 0 and pll_b_cr = 01. pclk would then be 40 mhz, epclk would then be 20 mhz, and the timer resolution would be 40 mhz/50, which is equal to 1.25 s. the sdram refresh rate would be 80 mhz/1200, which is equal to 15 s. another example using a different bclk frequency is bclk programmed to be 40 mhz, with pll_b_cr_slow = 1 (default) and pll_b_cr = 00 (default). pclk would then be 20 mhz, epclk would then be 40 mhz, and the timer resolution would be 20 mhz/12.5 which is equal to 0.625 s. the sdram refresh rate would be 40 mhz/300, which is equal to 7.5 s.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 12-3 12.4 timer registers memory map timer registers are identified in table 12-2. table 12-2. timer registers register label register name asb address type default value ref. tm_cnt1 timer 1 counter register 0x00350020 rw 0x00000000 12.5.1 tm_cnt2 timer 2 counter register 0x00350024 rw 0x00000000 12.5.2 tm_cnt3 timer 3 counter register 0x00350028 rw 0x00000000 12.5.3 tm_cnt4 timer 4 counter register 0x0035002c rw 0x00000000 12.5.4 tm_lmt1 timer 1 limit register 0x00350030 rw 0x00000000 12.5.5 tm_lmt2 timer 2 limit register 0x00350034 rw 0x00000000 12.5.6 tm_lmt3 timer 3 limit register 0x00350038 rw 0x00000000 12.5.7 tm_lmt4 timer 4 limit register 0x0035003c rw 0x00000000 12.5.8 12.5 timer registers 12.5.1 timer 1 counter register (tm_cnt1: 0x00350020) bit(s) type default name description 15:0 ro 16?b0 tm_cnt1 timer 1 current counter value. timer 1 increments every 1 s, from 0 to the timer 1 limit value, then resets to 0 and counts again. tm_cnt1 is reset whenever tm_lmt1 is written. 12.5.2 timer 2 counter register (tm_cnt2: 0x00350024) bit(s) type default name description 15:0 ro 16?b0 tm_cnt2 timer 2 current counter value. timer 2 increments every 1 s, from 0 to the timer 2 limit value, then resets to 0 and counts again. tm_cnt2 is reset whenever tm_lmt2 is written.
cx82100 home network processor data sheet 12-4 conexant proprietary and confidential information 101306c 12.5.3 timer 3 counter register (tm_cnt3: 0x00350028) bit(s) type default name description 15:0 ro 16?b0 tm_cnt3 timer 3 current counter value. timer 3 increments every 1 s, from 0 to the timer 3 limit value, then resets to 0 and counts again. tm_cnt3 is reset whenever tm_lmt3 is written. timer 3 can be used as a watchdog timer (see section 12.2). 12.5.4 timer 4 counter register (tm_cnt4: 0x0035002c) bit(s) type default name description 15:0 ro 16?b0 tm_cnt4 timer 4 current counter value. timer 4 increments every 1 s, from 0 to the timer 4 limit value, then resets to 0 and counts again. tm_cnt4 is reset whenever tm_lmt4 is written. 12.5.5 timer 1 limit register (tm_lmt1: 0x00350030) bit(s) type default name description 15:0 rw 16?b0 tm_lmt1 timer 1 limit value. when the timer 1 current count reaches this limit value, the int_timer1 interrupt bit in the interrupt status register (int_stat) is set. the periodic timer interrupt event rate is = 1 mhz / (tm_lmt1 + 1). if tm_lmt1 is set to 0, tm_cnt1 remains reset. tm_cnt1 is reset whenever tm_lmt1 is written. 12.5.6 timer 2 limit register (tm_lmt2: 0x00350034) bit(s) type default name description 15:0 rw 16?b0 tm_lmt2 timer 2 limit value. when the timer 2 current count reaches this limit value, the int_timer2 interrupt bit in the interrupt status register (int_stat) is set. the periodic timer interrupt event rate is = 1 mhz / (tm_lmt2 + 1). if tm_lmt2 is set to 0, tm_cnt2 remains reset. tm_cnt2 is reset whenever tm_lmt2 is written.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 12-5 12.5.7 timer 3 limit register (tm_lmt3: 0x00350038) bit(s) type default name description 15:0 rw 16?b0 tm_lmt3 timer 3 limit value. when the timer 3 current count reaches this limit value, the int_timer3 interrupt bit in the interrupt status register (int_stat) is set. the periodic timer interrupt event rate is = 1 mhz / (tm_lmt3 + 1). if tm_lmt3 is set to 0, tm_cnt3 remains reset. tm_cnt3 is reset whenever tm_lmt3 is written. if 1?hf is written to the lower nibble, watchdog timer mode is enabled (see section 12.2). 12.5.8 timer 4 limit register (tm_lmt4: 0x0035003c) bit(s) type default name description 15:0 rw 16?b0 tm_lmt4 timer 4 limit value. when the timer 4 current count reaches this limit value, the int_timer4 interrupt bit in the interrupt status register (int_stat) is set. the periodic timer interrupt event rate is = 1 mhz / (tm_lmt4 + 1). if tm_lmt4 is set to 0, tm_cnt4 remains reset. tm_cnt4 is reset whenever tm_lmt4 is written.
cx82100 home network processor data sheet 12-6 conexant proprietary and confidential information 101306c this page is intentionally blank.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 13-1 13 clock generation interface description the clock generation (clkgen) block generates internal and external clocks using two programmable, fractional multiply phase locked loop (pll) blocks, fclk_pll and bclk_pll (figure 13-1). included in each block is the actual pll circuit with a voltage-controlled oscillator (vco) and post-pll generation logic which divides the output of each pll to create a series of sub-multiple clocks. clock generation operation is controlled by the pll bypass (pllbp) input pin and by three registers: fclk pll register (pll_f), bclk pll register (pll_b), and low power mode register (lpmr). pllbp input low selects pll normal mode (see section 13.1) and pllbp input high selects pll bypass mode for factory clock test operation (see section 13.7). the signals on the fclkio/gpio39 and bclkio/gpio38 pins are also controlled by the pllbp pin and by the gpio_sel7 and gpio_sel6 control bits in the gpio optional register (gpio_opt, see section 9.3.1), respectively. fclkio/gpio39 pin control is summarized in table 13-1 and bclkio/gpio38 pin control is summarized in table 13-2. when in pll bypass mode, the fclkio and bclkio pins are configured as inputs, and are divided and used in place of the pll outputs. when in pll normal mode, the fclkio and bclkio pins can be configured as outputs, and provide a means to indirectly observe the frequency of the internal clocks generated by the plls. table 13-1. fclkio/gpio39 pin usage control pllbp input pin voltage level gpio_sel7 bit in gpio option register (gpio_opt) signal on fclkio/gpio39 pin pin signal direction low 0 gpio39 1 i/o low 1 uclk 2o high don?t care xfclk 2i notes: 1. default at power up reset. 2. see figure 13-1. table 13-2. bclkio/gpio38 pin usage control pllbp input pin voltage level gpio_sel6 bit in gpio option register (gpio_opt) signal on bclkio/gpio38 pin pin signal direction low 0 gpio38 1 i/o low 1 epclk 2o high don?t care xbclk 2i notes: 1. default at power up reset. 2. see figure 13-1.
cx82100 home network processor data sheet 13-2 conexant proprietary and confidential information 101306c figure 13-1. clock generation block diagram pll fclk fclk pll pll fclk pll uclk (pll fclk/2) low power mode enable (lpm_en) xfclk on fclkio pll bypass mode (pll_bp pin fclk slow speed select (pll_f_cr_slow ) fclk uclk fclk generation logic (post fclk pll) uclk on fclkio pre-scaler divide by 3, 4, or 5 phase detector charge pump and loop filter vco phase detector divide by m.n output divider (divide by 2) output divider (divide by 4) 101545_064 divide by 2 divide by 4 0 1 0 1 0 1 pll_f prescale select (pll_f_pre) pll fclk/2 pll_bp usb interface (12 mhz) hl_clk usb clock rate indicate (pll_f_cr) pll bclk bclk pll pll bclk pll pclk (pll bclk/2) low power mode enable (lpm_en) pll bypass mode (pll_bp pin bclk generation logic (post bclk pll) pre-scaler divide by 3, 4, or 5 phase detector charge pump and loop filter vco phase detector divide by m.n output divider (divide by 2) output divider (divide by 4) divide by 2 divide by 4 0 1 0 1 pll_b prescale select (pll_b_pre) pll bclk/2 0 1 0 1 0 1 0 1 divide by 2 divide by 4 bclk slow speed select (pll_b_cr_slow ) low power mode clock divider xbclk on bclkio low power mode clock divider (lpm_clk_div) divide by 4 divide by 2 bclk pclk epclk divider (by 3, 4, or 5 or 1 or 2) epclk on bclkio epclk clock rate select (pll_b_cr) cx82110 hnp clki xfclk/2 xfclk/4 xbclk/2 xbclk/4
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 13-3 13.1 pll normal mode when input pin pllbp is low, the pll output clocks are generated based on an externally provided reference clock frequency on the clki pin, typically sourced from an external oscillator. the clki frequency can range from 20 mhz to 40 mhz, 50% duty cycle. fclk_pll creates a family of frequencies related to 12 mhz. fclk_pll is typically programmed to output 96, 120 144, or 168 mhz. the fclk output is used directly by the arm9tdmi core when programmed to asynchronous or synchronous modes (see arm documents). fclk is divided by 2 to create uclk for use by the usb interface. uclk is the clock reference for usb timing, which requires a multiple of 12 mhz, with a minimum frequency of 48 mhz. bclk_pll creates a family of frequencies related to 25 mhz. bclk_pll is typically programmed to output 50, 75 or 100 mhz. the bclk output is used directly as the asb bus clock. bclk is divided by 2 to create pclk for the apb bus, and epclk (25 mhz) for use by a separate ethernet phy device. fclk_pll and bclk_pll each employ an independently controlled m.n fractional divider in its pll feedback circuit in order to synthesize frequencies which are not integer multiples of the reference clock on clki. the hnp defaults its clocks to ?slow mode?, meaning both the bclk and fclk are operating at a slower frequency than is used in typical applications. this facilitates lower power consumption immediately following power-on-reset. typical applications will program the plls to output higher frequencies at an appropriate time, e.g., after usb enumeration. pins fclkio and bclkio can be configured to output clocks fclk and epclk, respectively, through the gpio option register (section 9.3.1). both pins default to gpio inputs immediately following power-on-reset. the fclk_pll and the bclk_pll are implemented using 16-bit delta sigma ( ? ) synthesizers. fclk_pll is programmed by writing to the appropriate bits in the pll_f register (see section 13.4.1) and bclk_pll is programmed by writing to the appropriate bits in the pll_b register (see section 13.4.2). pll operation is also controlled by the low power mode register (lpmr) (see section 13.4.3). 13.2 generated clocks the fclk pll and bclk pll generated clocks are described in table 13-3 and table 13-4, respectively. fclk pll and bclk pll generated clock frequencies for various programming options are listed in table 13-5 and table 13-6, respectively. all clocks are substituted with the jtag test clock (pin tck) when the hnp is in boundary scan or internal scan mode. the arm940t processor uses bclk in place of fclk when in fastbus mode, which is the default mode immediately following power-on-reset.
cx82100 home network processor data sheet 13-4 conexant proprietary and confidential information 101306c table 13-3. fclk pll generated clocks clock minimum frequency (mhz) maximum operating frequency (mhz) description fclk 96 168 arm940t fast clock input, asynchronous to bus clock. can have a lower minimum if the usb interface is not used. internal. fclk must be equal to or greater than bclk. uclk 48 84 usb timing reference; always one-half the frequency of fclk. must be a multiple of 12 mhz for proper usb operation. internal. optionally external, output on fclkio pin. udc 12 12 usb timing reference. must be 12 mhz for proper usb operation; uclk divided by number corresponding to pll_f_cr. internal. table 13-4. bclk pll generated clocks clock minimum frequency (mhz) maximum operating frequency (mhz) description bclk 25 100 asb clock. internal. can have a lower minimum if epclk is not used for 25 mhz. pclk 12.5 50 apb clock; always one-half the frequency of bclk and aligned to bclk falling edge. internal. epclk 25 25 miscellaneous timing reference, e.g., ethernet phy. optionally external; output on bclkio pin. can be different frequency for applications other than an ethernet phy clock. table 13-5. fclk pll generated clocks programming examples fclk speed select (pll_f_cr_slow) pll_f frequency fclk (arm) frequency uclk frequency (fclk/2) usb clock rate select (pll_f_cr) udc clock frequency notes 0 (normal) 96 mhz 96 mhz 48 mhz 00 ( 8) 12 mhz 0 (normal) 120 mhz 120 mhz 60 mhz 01 ( 10) 12 mhz 0 (normal) 144 mhz 144 mhz 72 mhz 10 ( 12) 12 mhz 0 (normal) 168 mhz 168 mhz 84 mhz 10 ( 14) 12 mhz 1 (slow) 96 mhz 48 mhz 48 mhz 00 ( 4) 12 mhz default at por 1 (slow) 120 mhz 60 mhz 60 mhz 01 ( 5) 12 mhz 1 (slow) 144 mhz 72 mhz 72 mhz 10 ( 6) 12 mhz 1 (slow) 168 mhz 84 mhz 84 mhz 10 ( 7) 12 mhz table 13-6. bclk pll generated clocks programming examples bclk speed select (pll_f_cr_slow) pll_b frequency bclk (asb) frequency pclk (apb) frequency (bclk/2) epclk clock rate select (pll_b_cr) epclk (xbclk) clock frequency notes 0 (normal) 75 mhz 75 mhz 37.5 mhz 00 ( 3) 25 mhz 0 (normal) 100 mhz 100 mhz 50 mhz 01 ( 4) 25 mhz 1 (slow) 50 mhz 25 mhz 12.5mhz 00 ( 1) 25 mhz default at por 1 (slow) 100 mhz 50 mhz 25 mhz 01 ( 2) 25 mhz
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 13-5 13.3 pll register memory map table 13-7. pll register memory map register label register name asb address type default value ref. pll_f fclk pll register 0x00350068 rw 0x18d04dea 13.4.1 pll_b bclk pll register 0x0035006c rw 0x184e2730 13.4.2 lpmr low power mode register 0x00350014 rw 0x00000000 13.4.3 13.4 pll registers 13.4.1 fclk pll register (pll_f: 0x00350068) pll_f register is used by the fclk pll to generated the desired fclk/uclk. bit(s) type default name description 31:29 reserved. 28 rw 1?b1 pll_f_cr_slow fclk slow speed select. 0 = normal fclk speed. 1 = slow fclk speed (one-half normal speed), fclk = uclk. (default) 27 ro 1?b1 pll_f_lk fclk pll lock status. 0 = fclk pll not locked. 1 = fclk pll locked (must be continuous 1 to indicate proper fclk pll operation). 26 rw 1?b0 pll_f_dds disable fclk ? ? ? ? synthesizer. 0 = enable fclk ? synthesizer and select fractional divides. (default) 1 = disable the fclk ? synthesizer and select integer-only divides. 25:24 rw 2?b00 pll_f_cr usb clock rate indicate. these bits indicate to the usb interface block the rate of uclk. for proper usb operation, uclk should be programmed to 48, 60, 72, or 84 mhz. 00 = uclk rate is 48 mhz. (default) 01 = uclk rate is 60 mhz. 10 = uclk rate is 72 mhz. 11 = uclk rate is 84 mhz. 23:22 rw 2?b11 pll_f_pre fclk reference input prescale divider select. 00 = reserved. 01 = divide by 5. (default) 10 = divide by 4. 11 = divide by 3. 21:16 rw 6?b010110 (22d) pll_f_int fclk 6-bit integer divide select. 0 = selects pll power-down state. 14d enables the pll for normal operation as a clock synthesizer. see 13.5. (default) 15:0 rw 16?h4dea (19946d) pll_f_frac fclk 16-bit fractional divide. see 13.5.
cx82100 home network processor data sheet 13-6 conexant proprietary and confidential information 101306c 13.4.2 bclk pll register (pll_b: 0x0035006c) pll_b register is used by the bclk pll to generated the desired clocks bclk/pclk/epclk. bit(s) type default name description 31:29 reserved. 28 rw 1?b1 pll_b_cr_slow bclk slow speed select. 0 = normal bclk speed. 1 = slow bclk speed (one-half normal speed). (default) 27 ro 1?b1 pll_b_lk bclk pll lock status. 0 = bclk pll not locked. 1 = bclk pll locked (must be continuous 1 to indicate proper bclk pll operation). 26 rw 1?b0 pll_b_dds disable bclk ? ? ? ? synthesizer. 0 = enable bclk ? synthesizer and select fractional divides. (default) 1 = disable the bclk ? synthesizer and select integer-only divides. 25:24 rw 2?b00 pll_b_cr epclk clock rate select divider. for pll_b_cr_slow = 0: 00 = bclk divided by 3. 01 = bclk divided by 4. 10 = bclk divided by 5. for pll_b_cr_slow = 1: 00 = bclk divided by 1. (default) 01 = bclk divided by 2. 10 = reserved. 23:22 rw 2?b01 pll_b_pre bclk reference input prescale divider select. 00 = reserved. 01 = divide by 5. (default) 10 = divide by 4. 11 = divide by 3. 21:16 rw 6?b001110 (14d) pll_b_int bclk 6-bit integer divide select. 0 = selects pll power-down state. 14d enables the pll for normal operation as a clock synthesizer. see 13.5. (default) 15:0 rw 16?h2730 (10032d) pll_b_frac bclk 16-bit fractional divide. see 13.5.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 13-7 13.4.3 low power mode register (lpmr: 0x00350014) bit(s) type default name description 31:16 rw 16'b0 lpm_clk_div low power mode clock divider. in low power mode, bclk operation is changed to: bclk = clki/(lpm_clk_div + 1)*2 for example, a bclk as slow as 270 hz can be generated using a 35.328 mhz clki as the input if low power mode is enabled (lpm_en = 1) and bclk slow speed is not selected (pll_b_cr_slow = 0 in the pll_b register). if both lpm_en and pll_b_cr_slow = 1, the clock frequency for bclk is additionally divided by 2. 15:1 reserved. 0rw 0 lpm_en low power mode enable. 0 = normal mode. 1 = enable low power mode, i.e., bclk operates as described in lpmr[31:16]. it also switches off fclk and uclk to the arm40t core and usb block. note: this control bit will not switch off or power-down the plls. to put the plls in a power-down state, the pll_f_int / pll_b_int values (bits [21:16] in pll_f and pll_b registers) must be 0.
cx82100 home network processor data sheet 13-8 conexant proprietary and confidential information 101306c 13.5 pll programming the pll output frequency synthesized is equal to: () 2 2 _ } _{ _ } _{ _ } _{ ) ( _ _ _ 16 + = frac x pll int x pll pre x pll mhz freq clki mhz freq output pll where x refers to f or b for the fclk and bclk plls, respectively. for proper operation, fclk must always be equal or greater than bclk. the divide ratio for each desired clock frequency is given by: () 2 _ } _{ _ } _{ ) ( _ _ } _{ 2 _ _ 16 frac x pll int x pll mhz freq clki pre x pll mhz freq desired ratio divide + = = at power-up and reset, both fclk and bclk and default to 48 mhz and 25 mhz, respectively, when using a 35.328 mhz clki input. table 13-8 shows some desired frequencies and the necessary parameters for programming the pll_f and the pll_b registers (assuming a 35.328 mhz input at clki. table 13-8. desired frequencies and programming parameters example clki frequency (mhz) prescaler desired frequency (mhz) divide ratio integer (dec.) fraction (dec.) pll output frequency (mhz) pll_register 1 35.328 5 75 21.229620 21 15048 74.99998125 0x00553ac8 2 35.328 3 96 16.304348 16 19946 96.00002344 0x00d04dea 3 35.328 4 100 22.644928 22 42266 100.000002 0x0196a51a 4 35.328 3 120 20.380435 20 24932 119.9999844 0x01d46164 5 35.328 3 144 24.456522 24 29919 144.0000352 0x02d874df 6 35.328 3 168 28.532608 28 34905 167.9999960 0x03dc8859
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 13-9 13.6 watchdog timer mode when timer 3 is in watchdog timer mode (see section 12.2), the pll registers are disabled from updates by apb writes. this guarantees uninterrupted clocking in the event a watchdog timer timeout and subsequent system reset occurs. there is, however, a time window when the plls can be updated. this occurs when the 7-bit counter that counts to 100 (incremented every int_tm3) is equal to 0 or 1. since this counter is cleared every time the tm_lmt3 is written, the time window for allowed pll updates is usually open. when the arm program is not running properly, the window will close, eventually cause a system reset. 13.7 pll bypass mode if pllbp is set high, the plls are bypassed and the hnp is in test-clock mode with clocks supplied from the fclkio and bclkio pins (figure 13-1). the clock provided by fclkio is called xfck and the clock provided by bclkio is called xbck. the clocking requirement is shown in table 13-9. table 13-9. clocking requirements clock maximum frequency (mhz) accuracy (ppm) duty cycle (%) description xfck 144 100 50 2 arm940t fast clock input xbck 100 100 50 2 asb clock in order to setup the test clock mode, configuration control bits must be loaded by pulsing the clki pin. the rising edge of clki saves the state of xfck and xbck into a control register (xbctl, xfctl) internal to the pll hardware (and not visible to the software). the clock used to bypass the vco in pll_b is created by the xor (xbck, xfck, and xbctl). the clock used to bypass the vco in pll_f is created by the xor (xfck, xbck, and xfctl). thus the two plls can be bypassed with independent clocks, but at only ? the maximum possible frequency, when the control bits are reset to zero. an internal test vco bypass clock can be generated at twice the frequency of the external pin clocks if the xbck and xfck are signaled in quadrature (90 degrees out of phase), and the appropriate control bit(s) is (are) activated (see figure 13-2). note that clki also serves as an active-high asynchronous reset for the pll post- dividers when pllbp is high, otherwise the por is used. the internal bus clocks will not progress until clki is reset low while in test-clock mode.
cx82100 home network processor data sheet 13-10 conexant proprietary and confidential information 101306c figure 13-2. clocks generated in the pll bypass mode 101545_063 pllbp bclk pclk rst clki xbctl=0 xbck xfck xfctl=1 vco bypass clock in pll_b fclk uclk vco bypass clock in pll_f input clocks internal clocks output clocks note: this figure assumes pll_x_cr_slow = 0.
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 14-1 14 register map summary most of the register set resides on the apb. these registers are accessible by the microcontroller directly (memory-mapped). they are also accessible by the host slave- mode interface indirectly (host pointer). 14.1 register type definition the register types are defined in table 14-1. all registers are not pre-fetchable, which would imply side effects from reads. this means that read or write accesses, sequential or not, may drive state-dependent state control. table 14-1. register type definition register type description ro read-only wo write-only rw read / write rw* read / write, but data may not be same as written at a later time. rr same as rw, but writing a 1 resets corresponding bit location, writing 0 has no effect. rwp read-only, write-only shared port, data written cannot be read. only accessible by dmac wd write-only, operates on other data entering register.
cx82100 home network processor data sheet 14-2 conexant proprietary and confidential information 101306c 14.2 interface registers sorted by supported function the cx82100 interface registers sorted by supported function are listed in table 14-2. table 14-2. cx82100 interface registers sorted by supported function register label register name asb address type default value ref. dmac registers dmac_1_ptr1 dmac 1 current pointer 1 0x00300000 rw* 0x00000000 4.5.1 dmac_2_ptr1 dmac 2 current pointer 1 0x00300004 ro 0x00000000 4.5.1 dmac_3_ptr1 dmac 3 current pointer 1 0x00300008 rw* 0x00000000 4.5.1 dmac_4_ptr1 dmac 4 current pointer 1 0x0030000c ro 0x00000000 4.5.1 dmac_5_ptr1 dmac 5 current pointer 1 0x00300010 rw* 0x00000000 4.5.1 dmac_6_ptr1 dmac 6 current pointer 1 0x00300014 rw* 0x00000000 4.5.1 dmac_7_ptr1 dmac 7 current pointer 1 0x00300018 rw* 0x00000000 4.5.1 dmac_8_ptr1 dmac 8 current pointer 1 0x0030001c rw* 0x00000000 4.5.1 dmac_9_ptr1 dmac 9 current pointer 1 0x00300020 rw* 0x00000000 4.5.1 dmac_10_ptr1 dmac 10 current pointer 1 0x00300024 rw* 0x00000000 4.5.1 dmac_11_ptr1 dmac 11 current pointer 1 0x00300028 rw* 0x00000000 4.5.1 *** reserved *** 0x0030002c dmac_1_ptr2 dmac 1 indirect/return pointer 2 0x00300030 rw* 0x00000000 4.5.4 dmac_2_ptr2 dmac 2 indirect/return pointer 2 0x00300034 rw* 0x00000000 4.5.4 dmac_3_ptr2 dmac 3 indirect/return pointer 2 0x00300038 rw* 0x00000000 4.5.4 dmac_4_ptr2 dmac 4 indirect/return pointer 2 0x0030003c rw* 0x00000000 4.5.4 dmac_5_ptr2 dmac 5 indirect/return pointer 2 0x00300040 rw* 0x00000000 4.5.4 *** reserved *** 0x00300044? 0x0030005c dmac_1_cnt1 dmac 1 buffer size counter 1 0x00300060 rw* 0x00000000 4.5.3 dmac_2_cnt1 dmac 2 buffer size counter 1 0x00300064 rw* 0x00000000 4.5.3 dmac_3_cnt1 dmac 3 buffer size counter 1 0x00300068 rw* 0x00000000 4.5.3 dmac_4_cnt1 dmac 4 buffer size counter 1 0x0030006c rw* 0x00000000 4.5.3 dmac_5_cnt1 dmac 5 buffer size counter 1 0x00300070 rw* 0x00000000 4.5.3 dmac_6_cnt1 dmac 6 buffer size counter 1 0x00300074 rw* 0x00000000 4.5.3 *** reserved *** 0x00300078? 0x0030007c dmac_9_cnt1 dmac 9 buffer size counter 1 0x00300080 rw* 0x00000000 4.5.3 dmac_10_cnt1 dmac 10 buffer size counter 1 0x00300084 rw* 0x00000000 4.5.3 dmac_11_cnt1 dmac 11 buffer size counter 1 0x00300088 rw* 0x00000000 4.5.3 *** reserved *** 0x0030008c? 0x00300090 dmac_2_cnt2 dmac 2 buffer size counter 2 0x00300094 wo 0x00000000 4.5.4 *** reserved *** 0x00300098 dmac_4_cnt2 dmac 4 buffer size counter 2 0x0030009c wo 0x00000000 4.5.4 *** reserved *** 0x003000a0? 0x003000fc dmac_12_ptr1 dmac 11 current pointer 1 0x00300100 rw* 0x00000000 4.5.1 dmac_13_ptr1 dmac 12 current pointer 1 0x00300104 rw* 0x00000000 4.5.1 *** reserved *** 0x00300108? 0x0030010c dmac_12_cnt1 dmac 11 buffer size counter 1 0x00300110 rw* 0x00000000 4.5.3 dmac_13_cnt1 dmac 12 buffer size counter 1 0x00300114 rw* 0x00000000 4.5.3 *** reserved *** 0x00300118? 0x00300124
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 14-3 table 16-2. cx82100 interface registers sorted by supported function (continued) register label register name asb address type default value ref. host interface registers hst_ctrl host control register 0x002d0000 rw 0x00000008 5.3.1 hst_rwst host master mode read-wait-state control register 0x002d0004 rw 0x00739ce7 5.3.2 hst_wwst host master mode write-wait-state control register 0x002d0008 rw 0x00739ce7 5.3.3 hst_xfer_cntl host master mode transfer control register 0x002d000c rw 0x00000000 5.3.4 hst_read_cntl1 host master mode read control register 1 0x002d0010 rw 0x00000000 5.3.5 hst_read_cntl2 host master mode read control register 2 0x002d0014 rw 0x00000000 5.3.6 hst_write_cntl1 host master mode write control register 1 0x002d0018 rw 0x00000000 5.3.7 hst_write_cntl2 host master mode write control register 2 0x002d001c rw 0x00000000 5.3.8 mstr_intf_width host master mode peripheral size 0x002d0020 rw 0x00000000 5.3.9 mstr_handshake host master mode peripheral handshake 0x002d0024 rw 0x00000000 5.3.10 hdma_src_addr host master mode dma source address 0x002d0028 rw 0x00000000 5.3.11 hdma_dst_addr host master mode dma destination address 0x002d002c rw 0x00000000 5.3.12 hdma_bcnt host master mode dma byte count 0x002d0030 rw 0x00000000 5.3.13 hdma_timers host master mode dma timers 0x002d0034 rw 0x00000000 5.3.14 external memory control register emcr external memory control register 0x00350010 rw 0x00000000 6.12.1 emac registers e_dma_1 emac 1 source/destination dma data register 0x00310000 rwp (don?t care) 7.11.1 e_na_1 emac 1 network access register 0x00310004 rw 0x80200000 7.11.3 e_stat_1 emac 1 status register 0x00310008 rw* 0x00000000 7.11.4 e_ie_1 emac 1 interrupt enable register 0x0031000c rw 0x00000000 7.11.6 e_lp_1 emac 1 receiver last packet register 0x00310010 rw* 0x00000000 7.11.5 e_mii_1 emac 1 mii management interface register 0x00310018 rw1 0x00000008 7.11.7 et_dma_1 emac 1 destination dma data register 0x00310020 rop (don?t care) 7.11.2 e_dma_2 emac 2 source/destination dma data register 0x00320000 rwp (don?t care) 7.11.1 e_na_2 emac 2 network access register 0x00320004 rw 0x80200000 7.11.3 e_stat_2 emac 2 status register 0x00320008 rw* 0x00000000 7.11.4 e_ie_2 emac 2 interrupt enable register 0x0032000c rw 0x00000000 7.11.6 e_lp_2 emac 2 receiver last packet register 0x00320010 rw* 0x00000000 7.11.5 e_mii_2 emac 2 mii management interface register 0x00320018 rw2 0x00000008 7.11.7 et_dma_2 emac 2 destination dma data register 0x00320020 rop (don?t care) 7.11.2 usb registers u0_dma usb source/destination dma data register 0 0x00330000 rwp (don?t care) 8.8.1 u1_dma usb source/destination dma data register 1 0x00330008 rwp (don?t care) 8.8.2 u2_dma usb source/destination dma data register 2 0x00330010 rwp (don?t care) 8.8.3 u3_dma usb source/destination dma data register 3 0x00330018 rwp (don?t care) 8.8.4 ut_dma usb destination dma data register 0x00330020 ro (don?t care) 8.8.5 u_cfg usb configuration data register 0x00330024 rw 0x00000000 8.8.6 u_idat usb interrupt data register 0x00330028 rw 0x00000000 8.8.7 u_ctr1 usb control register 1 0x0033002c rw 0x04000000 8.8.8 u_ctr2 usb control register 2 0x00330030 rw 0x00000000 8.8.9 u_ctr3 usb control register 3 0x00330034 rw 0x00000000 8.8.10 u_stat usb status 0x00330038 rr 0x00000000 8.8.11 u_ier usb interrupt enable register 0x0033003c rw 0x00000000 8.8.12 u_stat2 usb status register 2 0x00330040 rr 0x00000000 8.8.13 u_ier2 usb interrupt enable register 2 0x00330044 rw 0x00000000 8.8.14 ep0_in_tx_inc ep0_in transmit increment register 0x00330048 rw 0x00000000 8.9.1 ep0_in_tx_pend ep0_in transmit pending register 0x0033004c ro 0x00000000 8.9.2 ep0_in_tx_qwcnt ep0_in transmit qword count register 0x00330050 ro 0x00000000 8.9.3 1 note: the bit e_mii_1[1] is read only. 2 note: the bit e_mii_2[1] is read only.
cx82100 home network processor data sheet 14-4 conexant proprietary and confidential information 101306c table 16-2. cx82100 interface registers sorted by supported function (continued) register label register name asb address type default value ref. ep1_in_tx_inc ep1_in transmit increment register 0x00330054 rw 0x00000000 8.9.4 ep1_in_tx_pend ep1_in transmit pending register 0x00330058 ro 0x00000000 8.9.5 ep1_in_tx_qwcnt ep1_in transmit qword count register 0x0033005c ro 0x00000000 8.9.6 ep2_in_tx_inc ep2_in transmit increment register 0x00330060 rw 0x00000000 8.9.7 ep2_in_tx_pend ep2_in transmit pending register 0x00330064 ro 0x00000000 8.9.8 ep2_in_tx_qwcnt ep2_in transmit qword count register 0x00330068 ro 0x00000000 8.9.9 ep3_in_tx_inc ep3_in transmit increment register 0x0033006c rw 0x00000000 8.9.10 ep3_in_tx_pend ep3_in transmit pending register 0x00330070 ro 0x00000000 8.9.11 ep3_in_tx_qwcnt ep3_in transmit qword count register 0x00330074 ro 0x00000000 8.9.12 ep_out_rx_dec ep_out receive decrement register 0x00330078 rw 0x00000000 8.9.13 ep_out_rx_pend ep_out receive pending register 0x0033007c ro 0x00000000 8.9.14 ep_out_rx_qwcnt ep_out receive qword count register 0x00330080 ro 0x00000000 8.9.16 ep_out_rx_bufsize ep_out receive buffer size register 0x00330084 rw 0x00000000 8.9.15 u_csr usb control-status register 0x00330088 ro/wo 0x00000000 8.9.20 udc_tsr udc time stamp register 0x0033008c ro 0x00000000 8.8.15 udc_stat udc status register 0x00330090 ro 0x00000000 8.8.16 usb_rxtimer usb receive dma watchdog timer register 0x00330094 rw 0x00000000 8.9.17 usb_rxtimercnt usb receive dma watchdog timer counter register 0x00330098 ro 0x00000000 8.9.18 ep_out_rx_pendlevel ep_out receive pending interrupt level register 0x0033009c rw 0x00000000 8.9.19 timer registers tm_cnt1 timer 1 counter register 0x00350020 rw 0x00000000 12.5.1 tm_cnt2 timer 2 counter register 0x00350024 rw 0x00000000 12.5.2 tm_cnt3 timer 3 counter register 0x00350028 rw 0x00000000 12.5.3 tm_cnt4 timer 4 counter register 0x0035002c rw 0x00000000 12.5.4 tm_lmt1 timer 1 limit register 0x00350030 rw 0x00000000 12.5.5 tm_lmt2 timer 1 limit register 0x00350034 rw 0x00000000 12.5.6 tm_lmt3 timer 1 limit register 0x00350038 rw 0x00000000 12.5.7 tm_lmt4 timer 1 limit register 0x0035003c rw 0x00000000 12.5.8 gpio registers gpio_ism1 gpio interrupt sensitivity mode register 1 0x003500a0 rw 0x00000000 9.3.20 gpio_ism2 gpio interrupt sensitivity mode register 2 0x003500a4 rw 0x00000000 9.3.21 gpio_ism3 gpio interrupt sensitivity mode register 3 0x003500a8 rw 0x00000000 9.3.22 gpio_opt gpio option register 0x003500b0 rw 0x00000000 9.3.1 gpio_oe1 gpio output enable register 1 0x003500b4 rw 0x00002306 9.3.2 gpio_oe2 gpio output enable register 2 0x003500b8 rw 0x00000082 9.3.3 gpio_oe3 gpio output enable register 3 0x003500bc rw 0x00000000 9.3.4 gpio_data_in1 gpio data input register 1 0x003500c0 ro 0x00000000 9.3.5 gpio_data_in2 gpio data input register 2 0x003500c4 ro 0x00000000 9.3.6 gpio_data_in3 gpio data input register 3 0x003500c8 ro 0x00000000 9.3.7 gpio_data_out1 gpio data output register 1 0x003500cc rw 0x23062306 9.3.8 gpio_data_out2 gpio data output register 2 0x003500d0 rw 0x00960086 9.3.9 gpio_data_out3 gpio data output register 3 0x003500d4 rw 0x00000000 9.3.10 gpio_isr1 gpio interrupt status register 1 0x003500d8 rr 0x00000000 9.3.11 gpio_isr2 gpio interrupt status register 2 0x003500dc rr 0x00000000 9.3.12 gpio_isr3 gpio interrupt status register 3 0x003500e0 rr 0x00000000 9.3.13 gpio_ier1 gpio interrupt enable register 1 0x003500e4 rw 0x00000000 9.3.14 gpio_ier2 gpio interrupt enable register 2 0x003500e8 rw 0x00000000 9.3.15 gpio_ier3 gpio interrupt enable register 3 0x003500ec rw 0x00000000 9.3.16 gpio_ipc1 gpio interrupt polarity control register 1 0x003500f0 rw 0x00000000 9.3.17 gpio_ipc2 gpio interrupt polarity control register 2 0x003500f4 rw 0x00000000 9.3.18 gpio_ipc3 gpio interrupt polarity control register 3 0x003500f8 rw 0x00000000 9.3.19 emac register m2m_dma memory to memory dma data register 0x00350000 rwp 64?bx 10.3.1 m2m_cntl memory to memory dma transfer control/counter 0x00350004 rw 0x00000000 10.3.2 interrupt registers int_la interrupt level assignment register 0x00350040 rw 0x00000000 11.2.1 int_stat interrupt status register 0x00350044 rr 0x00000000 11.2.2
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 14-5 register label register name asb address type default value ref. int_setstat interrupt set status register 0x00350048 wo 0x00000000 11.2.3 int_msk interrupt mask register 0x0035004c rw 0x00000000 11.2.4 int_mstat interrupt mask status register 0x00350090 ro 0x00000000 11.2.5 low power and pll registers lpmr low power mode register 0x00350014 rw 0x00000000 13.4.3 pll_f fclk pll register 0x00350068 rw 0x18d04dea 13.4.1 pll_b bclk pll register 0x0035006c rw 0x184e2730 13.4.2
cx82100 home network processor data sheet 14-6 conexant proprietary and confidential information 101306c 14.3 interface registers sorted by address the cx82100 interface registers sorted by address are listed in table 14-3. table 14-3. cx82100 interface registers sorted by address register label register name asb address type default value ref. hst_ctrl host control register 0x002d0000 rw 0x00000008 5.3.1 hst_rwst host master mode read-wait-state control register 0x002d0004 rw 0x00739ce7 5.3.2 hst_wwst host master mode write-wait-state control register 0x002d0008 rw 0x00739ce7 5.3.3 hst_xfer_cntl host master mode transfer control register 0x002d000c rw 0x00000000 5.3.4 hst_read_cntl1 host master mode read control register 1 0x002d0010 rw 0x00000000 5.3.5 hst_read_cntl2 host master mode read control register 2 0x002d0014 rw 0x00000000 5.3.6 hst_write_cntl1 host master mode write control register 1 0x002d0018 rw 0x00000000 5.3.7 hst_write_cntl2 host master mode write control register 2 0x002d001c rw 0x00000000 5.3.8 mstr_intf_width host master mode peripheral size 0x002d0020 rw 0x00000000 5.3.9 mstr_handshake host master mode peripheral handshake 0x002d0024 rw 0x00000000 5.3.10 hdma_src_addr host master mode dma source address 0x002d0028 rw 0x00000000 5.3.11 hdma_dst_addr host master mode dma destination address 0x002d002c rw 0x00000000 5.3.12 hdma_bcnt host master mode dma byte count 0x002d0030 rw 0x00000000 5.3.13 hdma_timers host master mode dma timers 0x002d0034 rw 0x00000000 5.3.14 dmac_1_ptr1 dmac 1 current pointer 1 0x00300000 rw* 0x00000000 4.5.1 dmac_2_ptr1 dmac 2 current pointer 1 0x00300004 ro 0x00000000 4.5.1 dmac_3_ptr1 dmac 3 current pointer 1 0x00300008 rw* 0x00000000 4.5.1 dmac_4_ptr1 dmac 4 current pointer 1 0x0030000c ro 0x00000000 4.5.1 dmac_5_ptr1 dmac 5 current pointer 1 0x00300010 rw* 0x00000000 4.5.1 dmac_6_ptr1 dmac 6 current pointer 1 0x00300014 rw* 0x00000000 4.5.1 dmac_7_ptr1 dmac 7 current pointer 1 0x00300018 rw* 0x00000000 4.5.1 dmac_8_ptr1 dmac 8 current pointer 1 0x0030001c rw* 0x00000000 4.5.1 dmac_9_ptr1 dmac 9 current pointer 1 0x00300020 rw* 0x00000000 4.5.1 dmac_10_ptr1 dmac 10 current pointer 1 0x00300024 rw* 0x00000000 4.5.1 dmac_11_ptr1 dmac 11 current pointer 1 0x00300028 rw* 0x00000000 4.5.1 *** reserved *** 0x0030002c dmac_1_ptr2 dmac 1 indirect/return pointer 2 0x00300030 rw* 0x00000000 4.5.4 dmac_2_ptr2 dmac 2 indirect/return pointer 2 0x00300034 rw* 0x00000000 4.5.4 dmac_3_ptr2 dmac 3 indirect/return pointer 2 0x00300038 rw* 0x00000000 4.5.4 dmac_4_ptr2 dmac 4 indirect/return pointer 2 0x0030003c rw* 0x00000000 4.5.4 dmac_5_ptr2 dmac 5 indirect/return pointer 2 0x00300040 rw* 0x00000000 4.5.4 *** reserved *** 0x00300044? 0x0030005c dmac_1_cnt1 dmac 1 buffer size counter 1 0x00300060 rw* 0x00000000 4.5.3 dmac_2_cnt1 dmac 2 buffer size counter 1 0x00300064 rw* 0x00000000 4.5.3 dmac_3_cnt1 dmac 3 buffer size counter 1 0x00300068 rw* 0x00000000 4.5.3 dmac_4_cnt1 dmac 4 buffer size counter 1 0x0030006c rw* 0x00000000 4.5.3 dmac_5_cnt1 dmac 5 buffer size counter 1 0x00300070 rw* 0x00000000 4.5.3 dmac_6_cnt1 dmac 6 buffer size counter 1 0x00300074 rw* 0x00000000 4.5.3 *** reserved *** 0x00300078? 0x0030007c dmac_9_cnt1 dmac 9 buffer size counter 1 0x00300080 rw* 0x00000000 4.5.3 dmac_10_cnt1 dmac 10 buffer size counter 1 0x00300084 rw* 0x00000000 4.5.3 dmac_11_cnt1 dmac 11 buffer size counter 1 0x00300088 rw* 0x00000000 4.5.3 *** reserved *** 0x0030008c? 0x00300090 dmac_2_cnt2 dmac 2 buffer size counter 2 0x00300094 wo 0x00000000 4.5.4 *** reserved *** 0x00300098 dmac_4_cnt2 dmac 4 buffer size counter 2 0x0030009c wo 0x00000000 4.5.4 *** reserved *** 0x003000a0? 0x003000fc
cx82100 home network processor data sheet 101306c conexant proprietary and confidential information 14-7 table 16-3. cx82100 interface registers sorted by address (continued) register label register name asb address type default value ref. dmac_12_ptr1 dmac 11 current pointer 1 0x00300100 rw* 0x00000000 4.5.1 dmac_13_ptr1 dmac 12 current pointer 1 0x00300104 rw* 0x00000000 4.5.1 *** reserved *** 0x00300108? 0x0030010c dmac_12_cnt1 dmac 11 buffer size counter 1 0x00300110 rw* 0x00000000 4.5.3 dmac_13_cnt1 dmac 12 buffer size counter 1 0x00300114 rw* 0x00000000 4.5.3 *** reserved *** 0x00300118? 0x00300124 e_dma_1 emac 1 source/destination dma data register 0x00310000 rwp (don?t care) 7.11.1 e_na_1 emac 1 network access register 0x00310004 rw 0x80200000 7.11.3 e_stat_1 emac 1 status register 0x00310008 rw* 0x00000000 7.11.4 e_ie_1 emac 1 interrupt enable register 0x0031000c rw 0x00000000 7.11.6 e_lp_1 emac 1 receiver last packet register 0x00310010 rw* 0x00000000 7.11.5 e_mii_1 emac 1 mii management interface register 0x00310018 rw3 0x00000008 7.11.7 et_dma_1 emac 1 destination dma data register 0x00310020 rop (don?t care) 7.11.2 e_dma_2 emac 2 source/destination dma data register 0x00320000 rwp (don?t care) 7.11.1 e_na_2 emac 2 network access register 0x00320004 rw 0x80200000 7.11.3 e_stat_2 emac 2 status register 0x00320008 rw* 0x00000000 7.11.4 e_ie_2 emac 2 interrupt enable register 0x0032000c rw 0x00000000 7.11.6 e_lp_2 emac 2 receiver last packet register 0x00320010 rw* 0x00000000 7.11.5 e_mii_2 emac 2 mii management interface register 0x00320018 rw4 0x00000008 7.11.7 et_dma_2 emac 2 destination dma data register 0x00320020 rop (don?t care) 7.11.2 u0_dma usb source/destination dma data register 0 0x00330000 rwp (don?t care) 8.8.1 u1_dma usb source/destination dma data register 1 0x00330008 rwp (don?t care) 8.8.2 u2_dma usb source/destination dma data register 2 0x00330010 rwp (don?t care) 8.8.3 u3_dma usb source/destination dma data register 3 0x00330018 rwp (don?t care) 8.8.4 ut_dma usb destination dma data register 0x00330020 ro (don?t care) 8.8.5 u_cfg usb configuration data register 0x00330024 rw 0x00000000 8.8.6 u_idat usb interrupt data register 0x00330028 rw 0x00000000 8.8.7 u_ctr1 usb control register 1 0x0033002c rw 0x04000000 8.8.8 u_ctr2 usb control register 2 0x00330030 rw 0x00000000 8.8.9 u_ctr3 usb control register 3 0x00330034 rw 0x00000000 8.8.10 u_stat usb status 0x00330038 rr 0x00000000 8.8.11 u_ier usb interrupt enable register 0x0033003c rw 0x00000000 8.8.12 u_stat2 usb status register 2 0x00330040 rr 0x00000000 8.8.13 u_ier2 usb interrupt enable register 2 0x00330044 rw 0x00000000 8.8.14 ep0_in_tx_inc ep0_in transmit increment register 0x00330048 rw 0x00000000 8.9.1 ep0_in_tx_pend ep0_in transmit pending register 0x0033004c ro 0x00000000 8.9.2 ep0_in_tx_qwcnt ep0_in transmit qword count register 0x00330050 ro 0x00000000 8.9.3 ep1_in_tx_inc ep1_in transmit increment register 0x00330054 rw 0x00000000 8.9.4 ep1_in_tx_pend ep1_in transmit pending register 0x00330058 ro 0x00000000 8.9.5 ep1_in_tx_qwcnt ep1_in transmit qword count register 0x0033005c ro 0x00000000 8.9.6 ep2_in_tx_inc ep2_in transmit increment register 0x00330060 rw 0x00000000 8.9.7 ep2_in_tx_pend ep2_in transmit pending register 0x00330064 ro 0x00000000 8.9.8 ep2_in_tx_qwcnt ep2_in transmit qword count register 0x00330068 ro 0x00000000 8.9.9 ep3_in_tx_inc ep3_in transmit increment register 0x0033006c rw 0x00000000 8.9.10 ep3_in_tx_pend ep3_in transmit pending register 0x00330070 ro 0x00000000 8.9.11 ep3_in_tx_qwcnt ep3_in transmit qword count register 0x00330074 ro 0x00000000 8.9.12 ep_out_rx_dec ep_out receive decrement register 0x00330078 rw 0x00000000 8.9.13 ep_out_rx_pend ep_out receive pending register 0x0033007c ro 0x00000000 8.9.14 ep_out_rx_qwcnt ep_out receive qword count register 0x00330080 ro 0x00000000 8.9.16 ep_out_rx_bufsize ep_out receive buffer size register 0x00330084 rw 0x00000000 8.9.15 3 note: the bit e_mii_1[1] is read only. 4 note: the bit e_mii_2[1] is read only.
cx82100 home network processor data sheet 14-8 conexant proprietary and confidential information 101306c table 16-3. cx82100 interface registers sorted by address (continued) register label register name asb address type default value ref. u_csr usb control-status register 0x00330088 ro/wo 0x00000000 8.9.20 udc_tsr udc time stamp register 0x0033008c ro 0x00000000 8.8.15 udc_stat udc status register 0x00330090 ro 0x00000000 8.8.16 usb_rxtimer usb receive dma watchdog timer register 0x00330094 rw 0x00000000 8.9.17 usb_rxtimercnt usb receive dma watchdog timer counter register 0x00330098 ro 0x00000000 8.9.18 ep_out_rx_pendlevel ep_out receive pending interrupt level register 0x0033009c rw 0x00000000 8.9.19 *** reserved *** 0x00340000? 0x00340080 m2m_dma memory to memory dma data register 0x00350000 rwp 64?bx 10.3.1 m2m_cntl memory to memory dma transfer control/counter 0x00350004 rw 0x00000000 10.3.2 emcr external memory control register 0x00350010 rw 0x00000000 6.12.1 lpmr low power mode register 0x00350014 rw 0x00000000 13.4.3 tm_cnt1 timer 1 counter register 0x00350020 rw 0x00000000 12.5.1 tm_cnt2 timer 2 counter register 0x00350024 rw 0x00000000 12.5.2 tm_cnt3 timer 3 counter register 0x00350028 rw 0x00000000 12.5.3 tm_cnt4 timer 4 counter register 0x0035002c rw 0x00000000 12.5.4 tm_lmt1 timer 1 limit register 0x00350030 rw 0x00000000 12.5.5 tm_lmt2 timer 1 limit register 0x00350034 rw 0x00000000 12.5.6 tm_lmt3 timer 1 limit register 0x00350038 rw 0x00000000 12.5.7 tm_lmt4 timer 1 limit register 0x0035003c rw 0x00000000 12.5.8 int_la interrupt level assignment register 0x00350040 rw 0x00000000 11.2.1 int_stat interrupt status register 0x00350044 rr 0x00000000 11.2.2 int_setstat interrupt set status register 0x00350048 wo 0x00000000 11.2.3 int_msk interrupt mask register 0x0035004c rw 0x00000000 11.2.4 pll_f fclk pll register 0x00350068 rw 0x18d04dea 13.4.1 pll_b bclk pll register 0x0035006c rw 0x184e2730 13.4.2 int_mstat interrupt mask status register 0x00350090 ro 0x00000000 11.2.5 gpio_ism1 gpio interrupt sensitivity mode register 1 0x003500a0 rw 0x00000000 9.3.20 gpio_ism2 gpio interrupt sensitivity mode register 2 0x003500a4 rw 0x00000000 9.3.21 gpio_ism3 gpio interrupt sensitivity mode register 3 0x003500a8 rw 0x00000000 9.3.22 gpio_opt gpio option register 0x003500b0 rw 0x00000000 9.3.1 gpio_oe1 gpio output enable register 1 0x003500b4 rw 0x00002306 9.3.2 gpio_oe2 gpio output enable register 2 0x003500b8 rw 0x00000082 9.3.3 gpio_oe3 gpio output enable register 3 0x003500bc rw 0x00000000 9.3.4 gpio_data_in1 gpio data input register 1 0x003500c0 ro 0x00000000 9.3.5 gpio_data_in2 gpio data input register 2 0x003500c4 ro 0x00000000 9.3.6 gpio_data_in3 gpio data input register 3 0x003500c8 ro 0x00000000 9.3.7 gpio_data_out1 gpio data output register 1 0x003500cc rw 0x23062306 9.3.8 gpio_data_out2 gpio data output register 2 0x003500d0 rw 0x00960086 9.3.9 gpio_data_out3 gpio data output register 3 0x003500d4 rw 0x00000000 9.3.10 gpio_isr1 gpio interrupt status register 1 0x003500d8 rr 0x00000000 9.3.11 gpio_isr2 gpio interrupt status register 2 0x003500dc rr 0x00000000 9.3.12 gpio_isr3 gpio interrupt status register 3 0x003500e0 rr 0x00000000 9.3.13 gpio_ier1 gpio interrupt enable register 1 0x003500e4 rw 0x00000000 9.3.14 gpio_ier2 gpio interrupt enable register 2 0x003500e8 rw 0x00000000 9.3.15 gpio_ier3 gpio interrupt enable register 3 0x003500ec rw 0x00000000 9.3.16 gpio_ipc1 gpio interrupt polarity control register 1 0x003500f0 rw 0x00000000 9.3.17 gpio_ipc2 gpio interrupt polarity control register 2 0x003500f4 rw 0x00000000 9.3.18 gpio_ipc3 gpio interrupt polarity control register 3 0x003500f8 rw 0x00000000 9.3.19
notes
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